Introduction to the Zynq All Programmable SoC Architecture

Course Description

This course provides hardware and firmware engineers with the knowledge to effectively utilize a Zynq™ All Programmable System on a Chip (SoC). It covers the architecture of the ARM® Cortex™-A9 processor-based processing system (PS) and the integration of programmable logic (PL).

The course also details the individual components that comprise the PS, I/O peripherals, timers, and caching, as well as the DMA, interrupt, and memory controllers. Emphasis will be placed on effective access and usage of the PS DDR controller from

Release Date

August 2012

Level

Embedded Hardware and Firmware 3

Training Duration

1 day

Who Should Attend?

Hardware and firmware engineers who are interested in implementing a system on a chip using the Zynq All Programmable SoC and programmable logic.

Prerequisites

• FPGA design experience
• Completion of the Essentials of FPGA Design course or equivalent knowledge of Xilinx ISE® software implementation tools
• Basic understanding of C programming
• Basic understanding of microprocessors
• Some HDL modeling experience

Software Tools

• Xilinx ISE Design Suite: Embedded or System Edition 14.2

Hardware

• Architecture: Zynq-7000 All Programmable SoC*
• Demo board: Zynq-7000 All Programmable SoC ZC702 or Zed board*

* This course focuses on the Zynq-7000 All Programmable SoC. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.

Skills Gained

After completing this comprehensive training, you will know how to:

• Describe the architecture and components that comprise the Zynq All Programmable SoC processing system (PS)
• Evaluate a processing system (PS) and programmable logic (PL) AXI interface
• Identify the configuration options for the Zynq All Programmable SoC

Course Outline

Day 1

• Zynq All Programmable SoC Overview
• Inside the Application Processor Unit (APU)
• Processor Input/Output Peripherals
• Lab 1: Building a Zynq All Programmable SoC Platform
• Zynq All Programmable SoC Architecture Essentials
• Zynq All Programmable SoC PS/PL AXI Ports
• Lab 2: Integrating Programmable Logic on the Zynq All Programmable SoC
• Zynq All Programmable SoC Configuration
• Zynq All Programmable SoC Memory Resources
• Lab 3: Running and Debugging a Linux Application on the Zynq All Programmable SoC

Lab Descriptions

• Lab 1: Building a Zynq System on a Chip – Examine the process of using the PlanAhead™ and Xilinx Platform Studio (XPS) tools to create a simple processing system.
• Lab 2: Using DMA on the Zynq All Programmable SoC – Experiment with effectively using the PS DMA controller to move data between DDRx memory and a custom PL peripheral.
• Lab 3: Running and Debugging a Linux Application on the Zynq All Programmable SoC – Explore a software application executing under the Linux operating system on the Zynq All Programmable SoC.

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