Essentials of FPGA Design

Course Description

Build an effective FPGA design using synchronous design techniques, instantiate appropriate device resources, use proper HDL coding techniques, make good pin assignments, set basic XDC timing constraints, and use the Vivado™ Design Suite to build, synthesize, implement, and download a design.

Release Date

January 2013

Level

FPGA 2

Training Duration

2 days

Who should attend?

Digital designers who have a working knowledge of HDL (VHDL or Verilog) and who are new to Xilinx FPGAs

Prerequisites

• Working HDL knowledge (VHDL or Verilog)
• Digital design experience

Other Optional RELs

• Basic HDL Coding Techniques
• Virtex-6 and Spartan-6 FPGA HDL Coding Techniques

Software Tools

• Vivado System Edition 2012.4

Hardware

• Architecture: 7 series FPGAs**
• Demo board: Kintex™-7 FPGA KC705 board**

* Go to www.xilinx.com/training and click the FPGA Design link under Online Training to view these videos.
** This course focuses on the 7 series architecture. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

• Take advantage of the primary 7 series FPGA architecture resources
• Use the Project Manager to start a new project
• Identify the available Vivado IDE design flows (project based and non-project batch)
• Identify file sets (HDL, XDC, simulation)
• Analyze designs by using the cross-selection capabilities, Schematic viewer, and Hierarchical viewer
• Synthesize and implement an HDL design
• Utilize the available synthesis and implementation reports to analyze a design (utilization, timing, power, etc.)
• Build custom IP with the IP Library utility
• Make basic timing constraints (create_clock, set_input_delay, and set_output_delay)
• Use the primary Tcl-based reports (check_timing, report_clock_interaction, report_clock_networks, and report_timing_summary)
• Describe and analyze common STA reports
• Identify synchronous design techniques
• Describe how an FPGA is configured

Course Outline

Day 1

• Design Methodology Summary
• Basic FPGA Architecture
• Vivado IDE Features and Benefits
• Introduction to the Vivado Design Suite
• Vivado IDE Project Manager and IP Library
• Vivado IDE Tool Overview
• Lab 1: Vivado Tool Overview
• Vivado IDE Synthesis and Reports
• Vivado IDE Implementation and Static Timing Analysis
• Lab 2: Vivado Synthesis and Implementation

Day 2

• Designing with FPGA Resources
• Clocking Resources
• Lab 3: Designing with FPGA Resources
• Basic Timing Constraints (XDC)
• Timing Reports
• Lab 4: Basic XDC and Timing Reports
• Synchronous Design Techniques
• FPGA Configuration
• Appendix: SystemVerilog
• Appendix: Design Methodology
• Appendix: HDL Coding Techniques

Lab Descriptions

• Lab 1: Vivado Tool Overview – Create a project in the Vivado Design Suite. Add files, simulate, and elaborate the design. Review the available reports, analyze the design with the Schematic and Hierarchy viewers, and run a design rule check (DRC). Finally, assign some of the I/O pins using the IO Planner.
• Lab 2: Vivado Synthesis and Implementation – Synthesize and analyze the design with the Schematic viewer, review XDC timing constraints, and run basic static timing analysis using the check_timing and report_clock_utilization reports. Implement the design and analyze some timing critical paths with the Schematic viewer. Download the bitstream to the demonstration board.
• Lab 3: Designing with FPGA Resources – use the Xilinx Clocking Wizard to configure a clocking subsystem to provide various clock outputs and clock buffers to connect clock signals to global clock networks.
• Lab 4: Basic XDC and Timing Reports – Use the create_clock, set_input_delay, and set_output_delay timing constraints to improve design performance. Perform static timing analysis before and after implementation to validate the performance results.

Customer Reviews 

• I thought that the labs were really helpful for this course and the material was at a good level for a fundamentals course.
  
  
  
• Great class! Excellent instructor/student discourse, and the labs were very helpful.
  
  
  
• I enjoyed my experience at xilinx. I plan on trying to sign up for more classes in the future.