FPGA Power Optimization

Course Description

Attending the FPGA Power Optimization class will help you create a more power efficient FPGA design. This course can help you fit your design into a smaller FPGA, reduce your FPGA’s power consumption, or run your FPGA at a lower temperature.

In addition, by mastering the tools and design methodologies presented in this course, you will be able to create your design faster, shorten your development time, and lower development costs.

Release Date

September 2011

Level

FPGA 2

Training Duration

1 day

Who should attend?

FPGA designers with intermediate knowledge of HDL and some experience with the Xilinx ISE® software tools

Prerequisites

• Essentials of FPGA Design course or equivalent knowledge of FPGA architecture features; the Xilinx implementation software flow and implementation options; reading timing reports; basic FPGA design techniques; global timing constraints and the Constraints Editor
• Intermediate HDL knowledge (VHDL or Verilog)
• Solid digital design background

Recommended

• Designing for Performance course
• Basic FPGA Architecture: Memory and Clocking Resources

Software Tools

• Xilinx ISE Design Suite: Logic or System Edition 13.1

Hardware

• Architecture: 7 series FPGAs*
• Demo board: Virtex®-6 FPGA ML605 board*

* This course focuses on the Spartan-6 architecture. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.

Skills Gained

After completing this comprehensive training, you will know how to:

• Describe the power saving features of the 7 series FPGAs
• Use the Xilinx Power Estimator spreadsheet and the Power Analyzer to estimate your design’s power consumption
• Import Activity Rates to complete a dynamic power estimation
• Use synthesis and implementation options to reduce your design’s power consumption
• Use optimum HDL coding techniques and design practices to reduce your design’s power consumption

Course Outline

• FPGA Power Requirements
• Xilinx Power Estimator Spreadsheet (XPE)
• Lab 1: Power Estimation with XPE
• Xilinx Power Analyzer
• Lab 2: Power Estimation with XPA
• Lab 3: Dynamic Power Estimation
• Power Management Software Options
• Lab 4: Power Management Software Options
• Power Management Design Techniques
• Power Optimization of I/O Resources
• 7 Series Power Management Features
• How to Solve a Power Problem
• Worse-Case Thermal Calculations (optional)
• Spartan-6 FPGA Power Management Features (optional)

Lab Descriptions

• Lab 1: Power Estimation with XPE – Estimate the resources required based on the high-level design description. Enter the amount of resources and default activity rates for the design and evaluate the estimated power calculated by XPE.
• Lab 2: Power Estimation with XPA –  Import the MAP report contents into the XPE spreadsheet and evaluate the estimated power with the XPE. Estimate the design’s power consumption with the XPA power estimation utility and compare its results to that made with XPE.
• Lab 3: Dynamic Power Estimation – Simulate the design with ISim and generate the necessary Switching Activity Interchange Format (SAIF) file. Launch the XPA utility, load the SAIF file contents, and use XPA to estimate your design’s dynamic power consumption.
• Lab 4: Power Management Software Options – Use the Power reduction option in MAP and the Global Optimization settings to save power in your design.

Customer Reviews 

• This is a new course; reviews will be posted as they are submitted.