Free Online FPGA Design Training
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Online video-based FPGA, DSP and Embedded design training courses available 24x7 at no charge. Topics range from high-level software updates and ASIC to FPGA conversion strategies to specifics on device architecture and coding techniques. Check one out today!
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Vivado "How To" Video-based Tutorials Xilinx is developing QuickTake Video Tutorials in order to assist our users in making the transition from the ISE software tools to the Vivado™ Design Suite. The tutorials are designed to be short clips targeting very specific topics. We’ll continue to add additional videos as well as keep the existing ones current as new software releases roll out. |
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Zynq "How To" and Informational Video-based Tutorials Xilinx is developing Zynq Video Tutorials. The tutorials are designed to be short clips targeting very specific topics. We’ll continue to add additional videos. Released: Oct 2012 |
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 Accelerating DSP Design Productivity with All Programmable FPGAs & SOCsDesigners tasked with delivering more capability and performance in today's sophisticated DSP applications are increasingly turning to programmable logic for their hardware solutions. Xilinx® 7 series FPGAs meet this demand with a family of devices uniquely developed to address specific market needs including high performance, low cost, and low power. Xilinx 7 series DSP design platforms accelerate development of DSP applications by reducing schedule risk, enabling design reuse, and introducing new high-level design methodologies. More Released: March 2013 |
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Reducing System Power & Cost with Artix-7 FPGAs In this video you will learn about overall system power and cost with Artix-7 FPGAs. We’ll quickly review the Artix-7 FPGA architecture, logic fabric, 4th gen DSP48E1 slice, 6.6 Gbps GTP transceivers, PCIe Gen2 hard block, memory interface, analog interface, applications overview, and where you can learn more. More Released: Feb 2013 |
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7-Series CLB Architecture This video introduces the 7-Series CLB architecture, including: LUTs, flip-flops, dedicated muxes, carry chain, and other resources. More Updated: Sept 2012 |
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7-Series Dedicated Hardware This video introduces the dedicated hardware resources available in the 7-Series FPGAs. The features described include the dedicated Serial Gigabit Transceivers, PCI Express core, and XADC resources. More Updated: Sept 2012 |
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7-Series DSP Resources This video introduces the DSP slice features of the 7-Series FPGAs. In addition discusses the Pre-Adder and Dynamic Pipeline control resources.More Updated: Sept 2012 |
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7-Series FPGA Overview A high-level introduction to the 7-Series product family and all of its device features. More Updated: Sept 2012 |
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7-Series Slice Flip Flops This video introduces slice flip-flop resources in the 7-Series FPGAs. Discussing the implications of how you design for your device flip-flop control signal resources and how your HDL coding style affects the speed and device utilization of your design. More Updated: Sept 2012 |
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7-Series Memory Controllers This video introduces the soft IP available for building memory controllers in the 7-Series FPGAs. These modules discuss how to build your memory controller with the Xilinx Memory Interface Generator and how the MIG can build a memory controller for DDR2, DDR3, mobile DRAM, and other memory types. More Updated: Sept 2012 |
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7-Series Memory Resources Learn how to describe the dedicated block memory resources in the 7-Series FPGAs, describe the different block memory modes available, describe the capabilities of the built in FIFO. More Updated: Sept 2012 |
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7-Series Clocking Resources Learn the details of the dedicated 7-Series clocking resource. After completing this module, you will be able to describe the available clock routing resources, and the capabilities of the Clock Management Tile (CMT) and PLLs. More Updated: Sept 2012 |
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Virtex-6 Memory Resources Learn how to fully utilize the Virtex®-6 distributed memory, block memory, and FIFO resources, use the Memory Interface Generator (MIG) to build a custom memory controller for your off-chip memory component. More Updated: Sept 2012 |
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Virtex-6 Slice and I/O Resources Learn how to describe the basic slice and I/O resources available in Virtex-6 FPGAs. More Updated: Sept 2012 |
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Virtex-6 Clocking Resources Learn how to detail the clocking resources available in the Virtex-6 FPGA, specify the resources available in the Clock Management Tile (CMT), describe the basics of the PLL capabilities. More Updated: Sept 2012 |
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Spartan-6 Memory Resources Learn how to fully utilize the Spartan®-6 distributed and block memory resources, understand the features and limitations of the Spartan-6 dedicated memory controller block (MCB), use the Memory Interface Generator (MIG) to build your custom memory controller and design an appropriate interface to your off-chip memory component. More Updated: Sept 2012 |
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Spartan-6 Slice and I/O Resources Learn how to describe the basic slice and I/O resources available in Spartan-6 FPGAs. More Updated: Sept 2012 |
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Spartan-6 Clocking Resources Learn how to describe the global and I/O clock networks in the Spartan-6 FPGA, describe the clock buffers and their relationships to the I/O resources, describe the DCM capabilities in the Spartan-6 FPGA. More Updated: Sept 2012 |
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Virtex-6 & Spartan-6 FPGA HDL Coding Techniques Learn how to code your register resources so your design will have fewer control sets and run at a higher system speed, avoid the most common coding mistakes that reduce device utilization and system speed, anticipate how your design will map to the register resources, code your design so you can infer more of the dedicated hardware resources, avoid the most common coding mistakes which hurt device utilization, reduce your dependence on global resets by taking advantage of the Global Set/Reset net (GSR). More Updated: Sept 2012 |
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Virtex-5 FPGA HDL Coding Techniques Learn how to code properly for Virtex-5 FPGA register resources. You will also know how to manage your control signal usage so that you can build a smaller FPGA design that will run at the highest system speed possiblel, code properly for 6-input LUT and block RAM resources in the Virtex-5 FPGA. You will also know how to manage your control signal usage so that you can build a high-speed FPGA design. Finally, you will identify the most important considerations for migrating an existing design to the Virtex-5 FPGA. More Updated: Sept 2012 |
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Spartan-3 FPGA HDL Coding Techniques Learn how to code properly for FPGA registers, SRLs, and other dedicated resources. These techniques will enable you to build an efficient, high-speed FPGA design for the Spartan-3 FPGA and other 4-input, LUT-based FPGAs. code properly for carry logic and memory resources. You will also know how to manage your control signal usage so that you can build an efficient, high-speed FPGA design for the Spartan-3 FPGA and other 4-input, LUT-based FPGAs. More Updated: Sept 2012 |
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What is the Difference Between an FPGA and an ASIC Learn how to describe the differences between ASIC and FPGA architectures, explain the features of Xilinx FPGA architecture, realize the benefit from Xilinx dedicated resources. More Updated: Aug 2012 |
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FPGA vs. ASIC Design Flow Learn how to desribe the differences between ASIC and FPGA Design flows including: design methodology, verification techniques, test-generation logic and tools. More Updated: Aug 2012 |
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How to Convert ASIC Code to FPGA Code Learn how to optimize ASIC code for implementation in an FPGA and describe the steps to perform ASIC to FPGA code conversion. More Updated: Aug 2012 |
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7-Series CLB Architecture This video introduces the 7-Series CLB architecture, including: LUTs, flip-flops, dedicated muxes, carry chain, and other resources. More Updated: Sept 2012 |
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7-Series Dedicated Hardware This video introduces the dedicated hardware resources available in the 7-Series FPGAs. The features described include the dedicated Serial Gigabit Transceivers, PCI Express core, and XADC resources. More Updated: Sept 2012 |
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7-Series DSP Resources This video introduces the DSP slice features of the 7-Series FPGAs. In addition discusses the Pre-Adder and Dynamic Pipeline control resources.More Updated: Sept 2012 |
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7-Series FPGA Overview A high-level introduction to the 7-Series product family and all of its device features. More Updated: Sept 2012 |
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7-Series Slice Flip Flops This video introduces slice flip-flop resources in the 7-Series FPGAs. Discussing the implications of how you design for your device flip-flop control signal resources and how your HDL coding style affects the speed and device utilization of your design. More Updated: Sept 2012 |
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7-Series Memory Controllers This video introduces the soft IP available for building memory controllers in the 7-Series FPGAs. These modules discuss how to build your memory controller with the Xilinx Memory Interface Generator and how the MIG can build a memory controller for DDR2, DDR3, mobile DRAM, and other memory types. More Updated: Sept 2012 |
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7-Series Memory Resources Learn how to describe the dedicated block memory resources in the 7-Series FPGAs, describe the different block memory modes available, describe the capabilities of the built in FIFO. More Updated: Sept 2012 |
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7-Series Clocking Resources Learn the details of the dedicated 7-Series clocking resource. After completing this module, you will be able to describe the available clock routing resources, and the capabilities of the Clock Management Tile (CMT) and PLLs. More Updated: Sept 2012 |
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Virtex-6 Memory Resources Learn how to fully utilize the Virtex®-6 distributed memory, block memory, and FIFO resources, use the Memory Interface Generator (MIG) to build a custom memory controller for your off-chip memory component. More Updated: Sept 2012 |
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Virtex-6 Slice and I/O Resources Learn how to describe the basic slice and I/O resources available in Virtex-6 FPGAs. More Updated: Sept 2012 |
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Virtex-6 Clocking Resources Learn how to detail the clocking resources available in the Virtex-6 FPGA, specify the resources available in the Clock Management Tile (CMT), describe the basics of the PLL capabilities. More Updated: Sept 2012 |
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Spartan-6 Memory Resources Learn how to fully utilize the Spartan®-6 distributed and block memory resources, understand the features and limitations of the Spartan-6 dedicated memory controller block (MCB), use the Memory Interface Generator (MIG) to build your custom memory controller and design an appropriate interface to your off-chip memory component. More Updated: Sept 2012 |
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Spartan-6 Slice and I/O Resources Learn how to describe the basic slice and I/O resources available in Spartan-6 FPGAs. More Updated: Sept 2012 |
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Spartan-6 Clocking Resources Learn how to describe the global and I/O clock networks in the Spartan-6 FPGA, describe the clock buffers and their relationships to the I/O resources, describe the DCM capabilities in the Spartan-6 FPGA. More Updated: Sept 2012 |
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How to Configure an FPGA Learn how to describe the FPGA configuration pins, choose an appropriate FPGA configuration scheme, connect multiple FPGAs into a configuration daisy chain, and describe currently available prototyping hardware. More Updated: Sept 2012 |
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Architecture Wizard and I/O Planning Learn how to list at least two uses for the Architecture Wizard, identify two features of PinAhead, and create quality pin assignments for Xilinx FPGAs. More Updated: Sept 2012 |
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ChipScope Pro Software Overview (with Labs) Learn how to describe the value of the ChipScope™ Pro software, describe how it works, list available relevant cores, use the Core Generator and Core Inserter software, plan for debug, and debug with the ChipScope Pro software. Links to the labs are at the end of the recording. More Updated: Sept 2012 |
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Global Timing Constraints Learn how to apply global timing constraints to a simple synchronous design, use the Xilinx Constraints Editor to specify global timing constraints. More Updated: Sept 2012 |
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Timing Closure After completing this course you will be able to describe the overall flow for gaining timing closure, specify the key elements in achieving timing closure, describe the importance of your HDL coding style, explain the importance of using Cores in your design, list the most effective implementation options that can help you. More Updated: Sept 2012 |
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Achieving Timing Closure After completing this course you will be able to describe a flow for obtaining timing closure, interpret a timing report and determine the cause of timing errors, apply Timing Analyzer report options to create customized timing reports. More Updated: Sept 2012 |
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Synthesis Options Learn how to identify synthesis tool options that can be used to increase performance and/or reduce your design size, describe an approach to using your synthesis tool to obtain higher performance and gain timing closure, use XST to get the most out of your HDL. More Updated: Sept 2012 |
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XST Synthesis Options After completing this course on XST Synthesis Options you will be able to describe an approach to using XST synthesis options to obtain higher performance and gain timing closure, use XST to get the most out of your HDL. More Updated: Sept 2012 |
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Core Generator Software System Learn how to describe the differences between LogiCORE™ and AllianceCORE solutions, identify two benefits of using cores in your designs, create customized cores by using the CORE Generator software system GUI, instantiate cores into your HDL design, run behavioral simulation on a design that contains cores. More Updated: Sept 2012 |
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Reducing System Power & Cost with Artix-7 FPGAs In this video you will learn about overall system power and cost with Artix-7 FPGAs. We’ll quickly review the Artix-7 FPGA architecture, logic fabric, 4th gen DSP48E1 slice, 6.6 Gbps GTP transceivers, PCIe Gen2 hard block, memory interface, analog interface, applications overview, and where you can learn more. More Released: Feb 2013 |
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FPGA Power Estimation Learn how to list the three phases of the design cycle where power calculations can be performed, estimate power consumption by using the XPower Estimator spreadsheet, estimate power consumption by using the XPower software utility. More Updated: Sept 2012 |
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How Do I Plan to Power My FPGA After completing this course on FPGA Power Management you will be able to explain why you should target as much of the hard IP as possible, describe how your designs power consumption is dependent on your use of control signals, explain how some common design techniques can improve your designs power consumption, use the newest architecture features to improve your designs power consumption. More Updated: Sept 2012 |
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What are FPGA Power Management Design Techniques After completing this course on FPGA Power you will be able to explain how static power is different from dynamic power, describe the impact a smaller device geometry has on static power consumption, define the relationship between leakage current and junction temperature, describe some of the device data sheet information that pertains to power consumption. More Updated: Sept 2012 |
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What are FPGA Power Management Software Options After completing this course on FPGA Power Management Software Options you will be able to explain some of the built in features that are already built into the ISE software, use the XST, MAP, and PAR options to manage power consumption. More Updated: Sept 2012 |
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What are the Power Requirements of My FPGA After completing this course on FPGA Power Requirements you will be able to describe your FPGAs power requirements, explain how power is used in an FPGA, explain how your power consumption depends on BOTH your design and the FPGA device you have chosen, justify how power consumption in an ASIC is different than an FPGA, explain why you need to manage your power consumption. More Updated: Sept 2012 |
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What are FPGA Power Management HDL Coding Techniques After completing this course on FPGA Power Mangement HDL Techniques you will be able to explain how power is dependent on the HDL coding style you use, describe how your designs power consumption is dependent on your use of control signals, explain how some common design techniques can improve your designs power consumption, show how some common design techniques can improve your designs power consumption. More Updated: Sept 2012 |
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How Do I Get Started with PlanAhead? (Demo) This video describes the advantages of using the PlanAhead software flow and demonstrates how to start a new project. It also describes how many different design flows are supported with the PlanAhead software. More Released: Jun 2011 |
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How Do I Implement My Design With PlanAhead? (Demo) This video describes the advantages of using the PlanAhead software flow and demonstrates how to implement your design. More Released: Jun 2011 |
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Why You Should Use PlanAhead (Demo) This video describes the advantages of using the PlanAhead software flow and demonstrates how to start a new project. It also describes how many different design flows are supported with the PlanAhead software. More Released: Jun 2011 |
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How to Create Area Constraints with PlanAhead After completing this course on Area Constraints you will be able to add Pblocks to your design with the Hierarchy viewer, Schematic viewer, and the Timing Report generator. More Updated: Sept 2012 |
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What are The Benefits of Area Constraints After completing this course on Area Constraints you will be able to create effective Area Constraints using PlanAhead tool, identify Floorplanning Methodologies, avoid the most common design and synthesis mistakes during floorplanning, gain timing closure with the PlanAhead tool, place the dedicated hardware resources. More Updated: Sept 2012 |
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How to Resolve Routing Congestion Learn how to resolve routing congestion problems with the use of the PlanAhead software and area constraints. More Updated: Sept 2012 |
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Routing Optimization Design Techniques Learn the most common mistakes designers make that cause routing congestion. Learn to use the best design techniques that optimize your routing solutions before problems develop. More Updated: Sept 2012 |
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Embedded Design with the Xilinx Embedded Developer Kit If you are new to Embedded design with Xilinx FPGAs, this training will help you: start planning your design, understand the difference between Xilinx's FPGA architectures is essential if you are going to select an appropriate FPGA device family. After completing this training you will know how to: decidingly choose between a PowerPC® 440 and a MicroBlaze™ processor system, explain the primary tool functionality included with the Embedded Development Kit, explain the benefits of building an embedded design with an FPGA More Released: Feb 2011 |
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Embedded Design with the MicroBlaze Soft Processor Core If you are new to Embedded design with Xilinx FPGA's, this module will explain why you may want to use the MicroBlaze soft processor core in any of our FPGA families. It will aid in your understanding of MicroBlaze basics which will enable you to take full advantage of its features. After completing this training you will know how to explain how the utilities included with the Embedded Developers Kit (EDK) are optimized for MicroBlaze and explain how the Base System Builder makes it easy to build your embedded system. More Released: Feb 2011 |
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The MicroBlaze Microcontroller System Learn about the MicroBlaze Micrcontroller System. This video demonstrates how to use the new MicroBlaze MCS core delivered free with ISE WebPACK and ISE Logic Edition. Find out how to quickly and easily place a simple microcontroller system in your logic design without the need for an Embedded Design Suite license. More Released: Dec 2012 |
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Embedded Design with the PPC 440 Processor Core If you are new to Embedded design with Xilinx FPGA's, this module will explain why you may want to use the PowerPC 440 processor in the Virtex-5 FX FPGA family. After completing this training you will know how to: explain some of the benefits of the PPC 440 processor, explain how the utilities included with the Embedded Developers Kit (EDK) are optimized for the PPC 440 processor and explain how the Base System Builder makes it easy to make your embedded system. More Released: Feb 2011 |
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How to Convert a PLB-based EMBD System to an AXI-based System After completing this course you will be able to explain what the AXI protocol is, identify the advantages of the AXI protocol over a shared bus model, list the various AXI-based system architectural models. More Released: Feb 2011 |
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How to use the 3 AXI Configurations After completing this course on the 3 AXI Configurations you will be able to: list the three AXI system architectural models (configurations), name the five AXI channels, summarize the AXI valid/ready acknowledgement model, describe the operation of the AXI streaming protocol. More Released: Feb 2011 |
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Getting Started with System Generator Learn how to create a DSP design that includes memories and control using Simulink and implement that design into a Xilinx FPGA, design highly efficient FIR filters for Xilinx device architectures, and define fixed-point numeric precision abstractly using the Xilinx DSP blockset. More Download Lab Files (1.2MB zip) Released: Oct 2006 |
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What are FPGA Power Management HDL Coding Techniques After completing this course on FPGA Power Mangement HDL Techniques you will be able to explain how power is dependent on the HDL coding style you use, describe how your designs power consumption is dependent on your use of control signals, explain how some common design techniques can improve your designs power consumption, show how some common design techniques can improve your designs power consumption. More Updated: Sept 2012 |
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Virtex-6 & Spartan-6 FPGA HDL Coding Techniques Learn how to code your register resources so your design will have fewer control sets and run at a higher system speed, avoid the most common coding mistakes that reduce device utilization and system speed, anticipate how your design will map to the register resources, code your design so you can infer more of the dedicated hardware resources, avoid the most common coding mistakes which hurt device utilization, reduce your dependence on global resets by taking advantage of the Global Set/Reset net (GSR). More Updated: Sept 2012 |
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Virtex-5 FPGA HDL Coding Techniques Learn how to code properly for Virtex-5 FPGA register resources. You will also know how to manage your control signal usage so that you can build a smaller FPGA design that will run at the highest system speed possiblel, code properly for 6-input LUT and block RAM resources in the Virtex-5 FPGA. You will also know how to manage your control signal usage so that you can build a high-speed FPGA design. Finally, you will identify the most important considerations for migrating an existing design to the Virtex-5 FPGA. More Updated: Sept 2012 |
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Spartan-3 FPGA HDL Coding Techniques Learn how to code properly for FPGA registers, SRLs, and other dedicated resources. These techniques will enable you to build an efficient, high-speed FPGA design for the Spartan-3 FPGA and other 4-input, LUT-based FPGAs. code properly for carry logic and memory resources. You will also know how to manage your control signal usage so that you can build an efficient, high-speed FPGA design for the Spartan-3 FPGA and other 4-input, LUT-based FPGAs. More Updated: Sept 2012 |
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Basic HDL Coding Techniques Learn how to describe primary coding techniques for FPGAs, including basic design guidelines that successful FPGA designers follow and explain proper coding techniques for combinatorial and registered logic, describe primary coding techniques for FPGAs, including basic design guidelines that successful FPGA designers follow, as well as, Finite State Machine design and building pipeline stages. More Updated: Sept 2012 |
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Analog Mixed Signal Introductory Overview The AMS Introductory Overview training provides an overview of what Xilinx Analog Mixed Signal Solution is. This training also enumerates the benefits of integration of Programmable Analog to Digital Convertor in the Xilinx 7-Series FPGAs. More Updated: Sept 2012 |
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Analog Mixed Signal XADC Evaluation After completing this training, you will understand how the 7-series AMS Targeted Design Platform can be used to evaluate the XADC core in your design. This training also covers some advanced concepts which designers can leverage for configuring the XADC in their design. More Updated: Sept 2012 |
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Analog Mixed Signal HDL Design Flow After completing this training, you will be able to implement a Xilinx Analog to Digital Convertor (XADC) Core with the latest 7-series devices. This training also provides a front to back flow for designing with XADC core using the Project Navigator or PlanAhead software tools. More Updated: Sept 2012 |
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Analog Mixed Signal EDK Design Flow After completing this training, you will be able to implement a Xilinx Analog to Digital Convertor (XADC) Core with the latest 7-series and Zynq-7000 All Programmable SoC devices. This training also provides a front to back flow for designing with XADC core using the Embedded Development Kit (EDK) Suite tools. More Updated: Sept 2012 |
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Analog Mixed Signal Overview for Zynq An overview of Xilinx Analog Mixed Signal Technology available in the Zynq-7000 All Programmable SoC. You will gain an understanding of Analog Mixed Signal, and value of onboard AMS integration and review primary AMS use cases for the Zynq-7000 AP SoC. More Released: Jan 2013 |
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Analog Mixed Signal Tools Overview Learn about the available Analog Mixed Signal Tools for the Zynq-7000 All Programmable SoC. This training will help you aquire an understanding of core AMS features, the advantages of integrated analog as well as an overview of the available AMS tools for the Zynq-7000 AP SoC. More Released: Jan 2013 |
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Zynq Analog Mixed Signal Evaluator Demo This video provides a quick overview of the The Analog Mixed Signal Evaluator (AMS Evaluator) tool interface, features and functions. More Released: Jan 2013 |
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Zynq Analog Mixed Signal ChipScope Pro Demo This video provides a quick overview of using ChipScope Pro in ISE or Logic Analyzer in Vivado for Analog Mixed Signal Analysis on your Zynq Device. More Released: Jan 2013 |
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Zynq Analog Mixed Signal XADC Wizard Demo This video provides a quick overview of the interface, features and functions within the XADC Wizard available in both ISE and Vivado. This is a great tool for digital designers looking to instantiate a basic design. More Released: Jan 2013 |
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Consumer Market Segment Overview This training is intended for consumer systems designers who may be considering FPGA technology in their designs. Topics include: Xilinx at a Glance, Xilinx in Consumer Electronics, The CE Designer’s Challenge, The Xilinx Solution. |
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Consumer Digital Displays Overview This training is intended for consumer systems designers who may be considering FPGA technology in their designs. Topics include: Xilinx Enables Video Innovation, Digital Display Applications for FPGAs, The Xilinx Approach. |
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Automotive Market Overview In this training we will take a look at the automotive market dynamics, why programmable logic technology is a superior solution for automotive applications, and why the Xilinx solution is particularly well suited for the automotive space. We will also look at the key automotive applications in which Xilinx provides a targeted solution and also take at look at Xilinx Targeted Design Platforms. |
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Automotive Infotainment Overview In this training you will learn about the various infortainment applications, common challenges, FPGA Solutions, the targeted design platform and intel in-vehicle infotainment. |
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Automotive Driver Information In this training you will learn about the various driver information applications, common challenges, FPGA solutions, the targeted design platform, fully reconfigurable cluster and hybrid cluster. |
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Automotive Driver Assistance In this training you will learn about the various driver assistance applications, common challenges, fpga solutions, the targeted design platform and image processing. |
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Automotive Video, Graphics and Displays Overview In this training you will learn about the various video and graphics applications, FPGA solutions, the targeted design platform and an example of a flexible display system. |
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Automotive Image Processing & Recognition In this training you will learn about the various image processing and recognition applications, FPGA applications, FPGA vs DSP solutions and a lane departure warning system example. |
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Automotive Networking & Connectivity In this training you will learn about the various image processing and recognition applications, FPGA applications, FPGA vs DSP solutions and a lane departure warning system example. |
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