Designing with VHDL

Course Description

This comprehensive course is a thorough introduction to the VHDL language. The emphasis is on writing solid synthesizable code and enough simulation code to write a viable testbench. Structural, register transfer level (RTL), and behavioral coding styles are covered. This class addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. You will also learn best coding practices that will increase your overall VHDL proficiency and prepare you for the Advanced VHDL course.

In this three-day course, you will gain valuable hands-on experience.
Incoming students with little or no VHDL knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations.

Release Date

June 2014

Level

FPGA 1

Training Duration

3 days

Who Should Attend?

Engineers who want to use VHDL effectively for modeling, design, and synthesis of digital designs

Prerequisites
  • Basic digital design knowledge
Software Tools
  • Vivado® Design or System Editon 2014.1
Hardware
  • Architecture: N/A*
  • Demo board: Kintex®-7 FPGA KC605 board*

* This course does not focus on any particular architecture. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.

Skills Gained

After completing this training, you will know how to:

  • Implement the VHDL portion of coding for synthesis
    • Identify the differences between behavioral and structural coding styles
    • Distinguish coding for synthesis versus coding for simulation
    • Use scalar and composite data types to represent information
    • Use concurrent and sequential control structure to regulate information flow
    • Implement common VHDL constructs (Finite State Machines [FSMs], RAM/ROM data structures)
  • Simulate a basic VHDL design
    • Write a VHDL testbench and identify simulation-only constructs
  • Identify and implement coding best practices
    • Optimize VHDL code to target specific silicon resources within the Xilinx FPGA
  • Create and manage designs within the Vivado Design Suite environment
Course Outline

Day 1

  • The "Shape" of VHDL
  • Demo: Multiplexer
  • Lab 1: Using the Tools
  • Documentation in VHDL
  • Data Types
  • Concurrent Operations
  • Lab 2: Using Concurrent Statements
  • Processes and Variables
  • Lab 3: Designing a Simple Process

Day 2

  • Introduction to Testbenches
  • ISim Simulation Tool Basics
  • Lab 4: Simulating a Simple Design
  • Creating Memory
  • Lab 5: Building a Dual-Port Memory
  • Finite State Machines
  • Lab 6: Building a Moore Finite State Machine
  • Targeting Xilinx FPGAs
  • Lab 7: Xilinx Tool Flow

Day 3

  • Loops and Conditional Elaboration
  • Lab 8: Using Loops
  • Attributes
  • Functions and Procedures
  • Packages and Libraries
  • Lab 9: Building Your Own Package
  • Interacting with the Simulation
  • Writing a Good Testbench
  • Lab 10: Building a Meaningful Testbench
Lab Descriptions

The labs for this course provide a practical foundation for creating synthesizable RTL code. All aspects of the design flow are covered in the labs. You will write, synthesize, simulate, and implement all the labs. The focus of the labs is to write code that will optimally infer reliable and high-performance circuits.

Customer Reviews 
  • The instructor was very effective at explaining not only the material in the manual (the official VHDL and Xilinx stance on things) but also injecting his experience into the mix--telling us what is actually often done in industry, what he has or hasn't used very much, which points are particularly important, etc. I was very pleased with this and would recommend making sure that all the instructors for this class do this as well, since experience is really the biggest thing a live instructor can offer that I can't get by reading the slides in my own time. Thank you!
    Rating

  • Instructor used time to excellent advantage. Knows how to balance lab and lecture and breaks. Keeps students busy! Zero downtime in this class.
    Rating

  • The whiteboard sidebars emphasizing the real world aspects were extremely informative and valued.
    Rating

  • The instructor's knowledge of EE principles, and VHDL was excellent.
    Rating

  • I appreciate the high amount of content in this class. It made it well worth my time.
    Rating

  • The instructor was one of the best I have ever had. Very professional, organized, and excellent grasp of material. Stayed on track really well.
    Rating

  • The instructor is very knowledgeable in VHDL and kept the course interesting by providing funny anecdotal stories regarding the various course topics.
    Rating

To Register

For class schedules as well as tuition and registration information, please contact one of our Authorized Training Providers:

 
/csi/footer.htm