Video Training: Virtex-6 & Spartan-6 FPGA HDL Coding Techniques

Description

Duration: 01:04:19

After completing this course, you will know how to:

  • Code your register resources so your design will have fewer control sets and run at a higher system speed
  • Avoid the most common coding mistakes that reduce device utilization and system speed
  • Anticipate how your design will map to the register resources
  • Code your design so you can infer more of the dedicated hardware resources
  • Avoid the most common coding mistakes which hurt device utilization
  • Reduce your dependence on global resets by taking advantage of the Global Set/Reset net (GSR)
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