Course Description
This course provides the overall context and framework for the development cycle of FPGAs. For those uninitiated to FPGA design, this course will arm you with the proper planning techniques, strategy, and FPGA tool flow to get up and designing an FPGA design now. The flow will take you from behavioral specification to tuning specifications for the FPGA, synthesis, verification, and onto implementation and download. Throughout the design cycle, the various tools within the Vivado™ Design Suite are introduced.
Release Date
Janaury 2013
Level
FPGA 1
Training Duration
1 day
Who Should Attend?
Digital designers new to FPGA design who need to learn the FPGA design cycle and the major aspects of the Vivado Design Suite
Prerequisites
- Basic knowledge of the VHDL or Verilog language
- Digital design knowledge
Recommended RELs
Software Tools
- Vivado System Edition 2012.4
Hardware
- Architecture: 7 series FPGAs**
- Demo board: Kintex™-7 FPGA KC705 board**
* Go to www.xilinx.com/training and click the FPGA Design link under Online Training to view these videos.
** This course focuses on the 7 series architecture. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.
Skills Gained
After completing this comprehensive training, you will have the necessary skills to:
- Identify the project planning required for an FPGA design
- Use the project GUI flow
- Identify the supported design flows
- Analyze a design by utilizing the Schematic viewer and Hierarchical viewers
- Synthesize and implement a design
- Utilize the available reports to analyze a design
- Recognize the contents of a Tcl script for synthesizing, implementing, and creating basic timing reports
Course Outline
- Design Methodology Summary
- Project Planning
- Vivado IDE Overview and Projects
- Lab 1: Vivado IDE Projects
- Vivado Tool Flow
- Lab 2: Vivado Tool Flow
- I/O Pin Planning and Clock Constraints
- Lab 3: I/O Pin Planning and Clock Constraints
- ISim Simulator
- Lab 4: XSIM Simulator (VHDL or Verilog)
- Appendix: Design Methodology
- Appendix: HDL Coding Techniques
Lab Descriptions
- Lab 1: Vivado IDE Projects – Create a new Vivado IDE project and add design files to the project. Explore the Vivado IDE and its design analysis features (Schematic viewer and the Hierarchy viewer).
- Lab 2: Vivado Tool Flow – Browse the RTL Schematic viewer to analyze the design and evaluate the implemented design results with the reporting features included with the Vivado IDE.
- Lab 3: I/O Pin Planning and Clock Constraints – Make pin assignments and enter basic timing constraints with the Vivado IDE Constraints viewer. Perform noise analysis and download the completed bitstream to the evaluation board.
- Lab 4: XSIM Simulator – Explore the XSIM simulator included with the Vivado IDE. View the design's associated testbench and perform a brief RTL simulation.
To Register
For class schedules as well as tuition and registration information, please contact one of our Authorized Training Providers: