Course Description
This course will update experienced ISE® software users to utilize the Vivado™ Design Suite. Learn the underlying database and static timing analysis (STA) mechanisms. Utilize Tcl for navigating the design, creating Xilinx design constraints (XDC), and creating timing reports. Learn to make appropriate timing constraints for SDR, DDR, source-synchronous, and system-synchronous interfaces for your FPGA design.
Release Date
Janaury 2013
Level
FPGA 2
Training Duration
2 days
Who Should Attend?
Existing Xilinx ISE Design Suite FPGA designers
Prerequisites
- FPGA design experience
- Completion of the Essentials of FPGA Design, Designing for Performance, and Advanced FPGA Implementation courses or equivalent knowledge of Xilinx ISE software implementation tools, techniques, architecture, and FPGA design techniques. Completion of the Vivado Design Suite for ISE Project Navigator Users course is strongly recommended.
- Intermediate VHDL or Verilog knowledge
Recommended Prerequisites
Software Tools
- Vivado System Edition 2012.4
Hardware
- Architecture: 7 series FPGAs*
- Demo board: None*
* This course focuses on the 7 series architecture. Check with your local Authorized Training Provider for specifics or other customizations.
Skills Gained
After completing this comprehensive training, you will have the necessary skills to:
- Access primary objects from the design database and filter lists of objects using properties
- Describe setup and hold checks and describe the components of a timing report
- Create appropriate input and output delay constraints and describe timing reports that involve input and output paths
- Explain the impact that manufacturing process variations have on timing analysis and describe how min/max timing analysis information is conveyed in a timing report
- Describe all of the options available with the report_timing and report_timing_summary commands
- Describe the timing constraints required to constrain system-synchronous and source-synchronous interfaces
- Analyze a timing report to identify how to center the clock in the data eye
- Create scripts for the project-based and non-project batch design flows
Course Outline
Day 1
- Design Methodology Summary
- Vivado IDE Review
- Accessing the Design Database
- Lab 1: Vivado IDE Database
- Static Timing Analysis and Clocks
- Lab 2: Vivado IDE Clocks
- Inputs and Outputs
- Lab 3:I/O Constraints
- Timing Exceptions
- Lab 4: Timing Exceptions
Day 2
- Advanced Timing Analysis
- Advanced I/O Interface Constraints
- Lab 5: Advanced I/O Timing
- Project-Based and Non-Project Batch Design Flows
- Scripting Using Project-Based and Non-Project Batch Flows
- Lab 6a: Scripting in the Project-Based Flow
- Lab 6b: Scripting in the Non-Project Batch Flow
Lab Descriptions
- Lab 1: Vivado IDE Database – Utilize the Vivado IDE database to set properties on a design.
- Lab 2: Vivado IDE Clocks – Create complete XDC constraints for the clocking resources in a design. Implement the design and use the available clocking reports to verify results.
- Lab 3: I/O Constraints – Create input and output constraints for a source-synchronous design by using the Timing Constraints utility. You will also generate useful timing reports to verify the timing results.
- Lab 4: Timing Exceptions – Use the Timing Constraints window to enter timing exceptions in the XDC format. You will also generate a useful timing report to verify the timing results.
- Lab 5: Advanced I/O Timing – Make I/O timing constraints for a source-synchronous, double data rate (DDR) interface. Perform a static timing analysis of the interfaces to determine the optimal clock and data relationship for maximum setup and hold-time margin. Finally, adjust the data path delay to realize the optimal timing solution.
- Lab 6a: Scripting in the Project-Based Flow – Write Tcl commands in the project-based flow for the design process (from creating a new project through implementation).
- Lab 6b: Scripting in the Non-Project Batch Flow – Write Tcl commands in the non-project batch flow for the design process (from creating a new project through implementation).
To Register
For class schedules as well as tuition and registration information, please contact one of our Authorized Training Providers: