Instructor-led Classroom Training Schedule


Filter Courses By:
Region Domain Month  
FPGA Design
Connectivity Design
Embedded Design
DSP Design
Hardware Description Languages

Date Location / City Class Title (Click to Register) Price TC*
2017-12-11 NETHERLANDS Heesch Designing with 7 Series (2 days) 1450 EUR  18 
2017-12-11 MN Orono (Minneapolis) Embedded Systems Software Design (2 days) 1600 USD  16 
2017-12-11 CHINA Beijing Embedded Design with PetaLinux Tools (2 days) 400 USD 
2017-12-11 ITALY Milano Embedded Systems Design (2 days) 1600 EUR  18 
2017-12-11 Online Embedded Systems Software Design (4 sessions) 1600 EUR  18 
2017-12-11 CA - NORTHERN San Jose Zynq-7000 All Programmable SoC (2 days) 1600 USD  16 
2017-12-11 RUSSIA Moscow Embedded Design with PetaLinux Tools (2 days) 48900 RUB  10 
2017-12-11 OH Brecksville Designing with Verilog (2 days) 1600 USD  16 
2017-12-11 IN Bangalore High-Level Synthesis for Software Engineers (2 days) 600 USD 
2017-12-11 AUSTRIA Vienna Designing with Verilog (3 days) 2250 EUR  27 
2017-12-11 AUSTRIA Vienna Designing with Verilog (3 days) 2250 EUR  27 
2017-12-12 Online Zynq UltraScale+ MPSoC for the System Architect (2 sessions) 1400 USD  14 
2017-12-12 AUSTRIA Vienna Designing with System Verilog (2 days) 1500 EUR  18 
2017-12-13 CHINA Xi'an Vivado Design Suite Tool Flow (1 day) 100 USD 
2017-12-13 ISRAEL Petah-Tikva Designing with VHDL (4 days) 6075 ILS  20 
2017-12-13 KOREA S Seoul Connectivity Memory Interfaces (2 days) 570 USD 
2017-12-13 NJ - NORTHERN Parsippany Vivado Boot Camp Phase-2 Custom (3 days) 2700 USD  27 
2017-12-13 CA - NORTHERN San Jose Vivado Adopter Class Custom (3 days) 2400 USD  24 
2017-12-13 NJ - SOUTHERN Marlton Vivado Boot Camp Phase-2 Custom (3 days) 2700 USD  27 
2017-12-13 RUSSIA Moscow Designing with Verilog (3 days) 72900 RUB  15 
2017-12-13 IN Bangalore Zynq-7000 All Programmable SoC (2 days) 600 USD 
2017-12-14 CHINA Webex Zynq-7000 All Programmable SoC (2 days) 400 USD 
2017-12-14 Online Essentials of FPGA Design Vivado Custom (2 sessions) 1600 USD  16 
2017-12-14 AUSTRIA Vienna Advanced VHDL (2 days) 1500 EUR  18 
2017-12-14 AUSTRIA Vienna Verification with System Verilog (2 days) 1500 EUR  18 
2017-12-14 Online Embedded Systems Software Design (2 sessions) 1800 USD  18 
2017-12-18 MN Orono (Minneapolis) Designing with Verilog (3 days) 2400 USD  24 
2017-12-18 CHINA Shenzhen Embedded Systems Software Design (2 days) 400 USD 
2017-12-18 KOREA S Seoul Embedded Systems Design (2 days) 570 USD 
2017-12-18 ITALY Milano Embedded Systems Software Design (2 days) 1600 EUR  18 
2017-12-18 CHINA Xi'an Designing with 7 Series (2 days) 400 USD 
2017-12-18 Online Designing with Verilog and SystemVerilog Custom (5 sessions) 4000 USD  40 
2017-12-18 Online Designing with Verilog (3 sessions) 2400 USD  24 
2017-12-18 CHINA Shanghai Designing with Verilog (2 days) 300 USD 
2017-12-18 RUSSIA Moscow Designing with UltraScale FPGA Transceivers (2 days) 48900 RUB  10 
2017-12-18 Online UltraFast Design Methodology (2 sessions) 1600 USD  16 
2017-12-20 NETHERLANDS Heesch DSP Design Using System Generator (2 days) 1450 EUR  18 
2017-12-20 Online Designing with Verilog (4 sessions) 2400 EUR  20 
2017-12-20 CA - LOS ANGELES El Segundo Partial Reconfiguration (2 days) 1400 USD  14 
2017-12-20 AUSTRIA Vienna DSP Design Using System Generator (2 days) 1500 EUR  18 
2017-12-21 Online Designing with System Verilog (2 sessions) 1600 USD  16 
2017-12-21 CHINA Beijing Designing with the UltraScale Architecture (2 days) 400 USD 
2017-12-21 CHINA Shenzhen Partial Reconfiguration (2 days) 400 USD 
2017-12-21 MN Orono (Minneapolis) Partial Reconfiguration (2 days) 1800 USD  18 
2017-12-21 Online Designing FPGAs Using the Vivado Design Suite 2 (2 sessions) 1600 USD  16 
2017-12-21 MN Orono (Minneapolis) Designing with System Verilog (2 days) 1600 USD  16 
2017-12-24 ISRAEL Petah-Tikva Designing a LogiCORE PCI Express System (3 days) 4585 ILS  15 
2017-12-25 ISRAEL Petah-Tikva Designing with System Verilog (4 days) 6075 ILS  20 
2017-12-25 CHINA Webex Designing with the UltraScale Architecture (2 days) 400 USD 
2017-12-25 CHINA Shanghai Zynq-7000 All Programmable SoC (2 days) 400 USD 
2017-12-26 Online Essential Microprocessor Systems (1 session) 800 USD 
2017-12-26 MN Orono (Minneapolis) Essential Microprocessor Systems (1 day) 800 USD 
2017-12-27 Online Board Design for UltraScale Series FPGAs Custom (2 sessions) 800 USD 
2017-12-28 CHINA Shenzhen UltraFast Design Methodology (2 days) 400 USD 
2017-12-28 CHINA Shanghai Designing a LogiCORE PCI Express System (2 days) 400 USD 
2017-12-28 CHINA Beijing DSP Design Using System Generator (2 days) 400 USD 
2018-01-03 KOREA S Seoul Designing with Verilog (3 days) 600 USD 
2018-01-04 CHINA Shanghai UltraFast Design Methodology (2 days) 400 USD 
2018-01-07 CHINA Webex Designing with 7 Series (2 days) 400 USD 
2018-01-08 NETHERLANDS Heesch Embedded Systems Design (2 days) 1450 EUR  18 
2018-01-08 CHINA Webex Designing with the UltraScale Architecture (2 days) 400 USD 
2018-01-10 NETHERLANDS Heesch Embedded Systems Software Design (2 days) 1450 EUR  18 
2018-01-10 TAIWAN Taipei Embedded Systems Software Design (2 days) 20000 NTD 
2018-01-10 KOREA S Seoul Designing with Ethernet MAC Controllers (2 days) 570 USD 
2018-01-10 CHINA Beijing Vivado Design Suite Tool Flow (1 day) 100 USD 
2018-01-11 JAPAN Tokyo Essentials of FPGA Design Custom (2 days) 98000  
2018-01-11 CHINA Shanghai Zynq-7000 All Programmable SoC (2 days) 400 USD 
2018-01-15 KOREA S Seoul Zynq-7000 All Programmable SoC (2 days) 570 USD 
2018-01-15 RUSSIA Moscow Designing FPGAs Using the Vivado Design Suite 1 (3 days) 72900 RUB  15 
2018-01-15 CHINA Chengdu Designing with the UltraScale Architecture (2 days) 400 USD 
2018-01-16 AUSTRIA Vienna Designing with the UltraScale Architecture (2 days) 1500 EUR  18 
2018-01-16 AUSTRIA Vienna Designing with 7 Series (2 days) 1500 EUR  18 
2018-01-17 MD Columbia Vivado Boot Camp Phase-2 Custom (3 days) 2700 USD  27 
2018-01-17 TAIWAN Taipei Designing with the UltraScale Architecture (2 days) 20000 NTD 
2018-01-17 VA Sterling Vivado Boot Camp Phase-2 Custom (3 days) 2700 USD  27 
2018-01-17 CHINA Shenzhen Vivado Design Suite Tool Flow (1 day) 100 USD 
2018-01-18 CHINA Beijing Zynq-7000 All Programmable SoC (2 days) 400 USD 
2018-01-18 CHINA Shenzhen DSP Design Using System Generator (2 days) 400 USD 
2018-01-18 AUSTRIA Vienna Zynq-7000 All Programmable SoC (2 days) 1500 EUR  18 
2018-01-18 FL Florida Zynq-7000 All Programmable SoC (2 days) 1600 USD  16 
2018-01-22 CHINA Shanghai Designing with Ethernet MAC Controllers (2 days) 400 USD 
2018-01-22 AUSTRIA Vienna Partial Reconfiguration (2 days) 1500 EUR  18 
2018-01-22 NETHERLANDS Heesch Partial Reconfiguration (2 days) 1450 EUR  18 
2018-01-22 CHINA Beijing Embedded Systems Design (2 days) 400 USD 
2018-01-22 RUSSIA Moscow PCIe Protocol (1 day) 24900 RUB 
2018-01-22 Online PCI Express Protocol Custom (2 sessions) 800 USD 
2018-01-23 JAPAN Yokohama DSP Design Using System Generator (2 days) 98000  
2018-01-23 RUSSIA Moscow Designing a LogiCORE PCI Express System (2 days) 48900 RUB  10 
2018-01-24 NY - ROCHESTER Rochester Vivado Boot Camp Phase-1 Custom (3 days) 2700 USD  27 
2018-01-24 Online C-based design: High-Level Synthesis with Vivado HLx (2 sessions) 1400 USD  14 
2018-01-24 NETHERLANDS Heesch UltraFast Design Methodology (2 days) 1450 EUR  18 
2018-01-24 CHINA Webex Vivado Design Suite Tool Flow (1 day) Please Call
2018-01-25 IL - CHICAGO Schaumburg Partial Reconfiguration (2 days) 1800 USD  18 
2018-01-25 CHINA Beijing Designing with VHDL (2 days) 300 USD 
2018-01-25 Online Connectivity Memory Interfaces (2 sessions) 1600 USD  16 
2018-01-25 JAPAN Tokyo Zynq-7000 All Programmable SoC (2 days) 98000  
2018-01-27 KOREA S Seoul Embedded Design with PetaLinux Tools (3 days) 855 USD 
2018-01-29 CHINA Shanghai Embedded Design with PetaLinux Tools (2 days) 400 USD 
2018-01-29 NETHERLANDS Heesch Doulos Comprehensive VHDL Custom (5 days) 3595 EUR  54 
2018-01-29 NJ - NORTHERN Parsippany Vivado Boot Camp Phase-1 Custom (3 days) 2700 USD  27 
2018-01-29 NETHERLANDS Heesch Doulos VHDL for FPGA Design Custom (3 days) 2495 EUR  38 
2018-01-29 RUSSIA Moscow Zynq UltraScale+ MPSoC for the System Architect (2 days) 48900 RUB  10 
2018-01-29 AUSTRIA Vienna Embedded Open-Source Linux Development (3 days) 2250 EUR  27 
2018-01-29 MN Orono (Minneapolis) Xilinx HLS and SDSoC Custom (3 days) 2400 USD  24 
2018-01-29 AUSTRIA Vienna Embedded Systems Software Development (2 days) 1500 EUR  18 
2018-01-29 NJ - SOUTHERN Marlton Vivado Boot Camp Phase-1 Custom (3 days) 2700 USD  27 
2018-01-30 AUSTRIA Vienna Embedded Systems Design (2 days) 1500 EUR  18 
2018-01-30 JAPAN Tokyo Vivado Design Suite Tool Flow Custom (1 day) 49000  
2018-01-31 CHINA Shanghai Introduction to Zynq EPP Architecture (1 day) 100 USD 
2018-02-01 NETHERLANDS Heesch Doulos Advanced VHDL Custom (2 days) 1795 EUR  27 
2018-02-01 AUSTRIA Vienna Custom (2 days) 2250 EUR  18 
2018-02-05 NETHERLANDS Heesch Designing with 7 Series (2 days) 1450 EUR  18 
2018-02-05 AUSTRIA Vienna Designing with Multi-Gigabit Serial I/O (3 days) 2250 EUR  27 
2018-02-05 KOREA S Seoul Designing with VHDL (3 days) 600 USD 
2018-02-05 RUSSIA Moscow Designing with System Verilog (2 days) 48900 RUB  10 
2018-02-06 AUSTRIA Vienna Designing with UltraScale FPGA Transceivers (2 days) 1500 EUR  18 
2018-02-07 NY - NEW YORK METRO Hauppauge Designing with VHDL (3 days) 2700 USD  27 
2018-02-07 RUSSIA Moscow Designing with Ethernet MAC Controllers (2 days) 48900 RUB  10 
2018-02-08 KOREA S Seoul Embedded Systems Design (2 days) 570 USD 
2018-02-08 AUSTRIA Vienna Connectivity Memory Interfaces (2 days) 1500 EUR  18 
2018-02-08 JAPAN Tokyo Embedded Systems Design (2 days) 98000  
2018-02-08 AUSTRIA Vienna Custom (2 days) 1500 EUR  18 
2018-02-08 AUSTRIA Vienna Designing a LogiCORE PCI Express System (2 days) 1500 EUR  18 
2018-02-12 AUSTRIA Vienna Designing with Verilog (3 days) 2250 EUR  27 
2018-02-12 AUSTRIA Vienna Designing with Verilog (3 days) 2250 EUR  27 
2018-02-12 RUSSIA Moscow Designing FPGAs Using the Vivado Design Suite 2 (3 days) 72900 RUB  15 
2018-02-13 AUSTRIA Vienna Designing with System Verilog (2 days) 1500 EUR  18 
2018-02-14 JAPAN Tokyo Partial Reconfiguration (1 day) 49000  
2018-02-15 JAPAN Tokyo Essentials of FPGA Design Custom (2 days) 98000  
2018-02-15 AUSTRIA Vienna Advanced VHDL (2 days) 1500 EUR  18 
2018-02-15 AUSTRIA Vienna Verification with System Verilog (2 days) 1500 EUR  18 
2018-02-15 MN Orono (Minneapolis) Partial Reconfiguration (2 days) 1800 USD  18 
2018-02-19 NETHERLANDS Heesch Zynq-7000 All Programmable SoC (2 days) 1450 EUR  18 
2018-02-19 RUSSIA Moscow Embedded Systems Design (2 days) 48900 RUB  10 
2018-02-19 MN Orono (Minneapolis) DSP Design Using System Generator (2 days) 1600 USD  16 
2018-02-20 JAPAN Tokyo Designing a LogiCORE PCI Express System (2 days) 98000  
2018-02-20 KOREA S Seoul DSP Design Using System Generator (2 days) 570 USD 
2018-02-21 RUSSIA Moscow Verification with System Verilog (2 days) 48900 RUB  10 
2018-02-21 CO Longmont Embedded Systems Design (2 days) 1400 USD  14 
2018-02-21 AUSTRIA Vienna DSP Design Using System Generator (2 days) 1500 EUR  18 
2018-02-21 TAIWAN Taipei Embedded Systems Design (2 days) 20000 NTD 
2018-02-21 NY - ROCHESTER Rochester Vivado Boot Camp Phase-2 Custom (3 days) 2700 USD  27 
2018-02-22 KOREA S Seoul Designing a LogiCORE PCI Express System (2 days) 570 USD 
2018-02-26 NETHERLANDS Heesch Doulos Expert VHDL Custom (5 days) 3795 EUR  57 
2018-02-26 NETHERLANDS Heesch Doulos Expert VHDL Design Custom (2 days) 1945 EUR  29 
2018-02-27 JAPAN Yokohama UltraFast Design Methodology (2 days) 98000   10 
2018-02-27 AUSTRIA Vienna Designing with 7 Series (2 days) 1500 EUR  18 
2018-02-27 AUSTRIA Vienna Designing with the UltraScale Architecture (2 days) 1500 EUR  18 
2018-02-27 MD Columbia Vivado Boot Camp Phase-3 Custom (3 days) 3000 USD  30 
2018-02-28 JAPAN Tokyo Vivado Design Suite Tool Flow Custom (1 day) 49000  
2018-02-28 NETHERLANDS Heesch Doulos Expert VHDL Verification Custom (3 days) 2595 EUR  39 
2018-03-01 RUSSIA Moscow Designing FPGAs Using the Vivado Design Suite 3 (3 days) 72900 RUB  15 
2018-03-01 AUSTRIA Vienna Zynq-7000 All Programmable SoC (2 days) 1500 EUR  18 
2018-03-05 AUSTRIA Vienna Partial Reconfiguration (2 days) 1500 EUR  18 
2018-03-06 JAPAN Tokyo Essentials of FPGA Design Custom (2 days) 98000  
2018-03-06 Online TCL Custom (2 sessions) 1400 USD  14 
2018-03-07 NJ - NORTHERN Parsippany Vivado Boot Camp Phase-2 Custom (3 days) 2700 USD  27 
2018-03-07 NJ - SOUTHERN Marlton Vivado Boot Camp Phase-2 Custom (3 days) 2700 USD  27 
2018-03-07 NETHERLANDS Heesch Designing with Multi-Gigabit Serial I/O (3 days) 2175 EUR  27 
2018-03-07 TAIWAN Taipei Zynq-7000 All Programmable SoC (2 days) 20000 NTD 
2018-03-08 JAPAN Tokyo Embedded Systems Software Design (2 days) 98000  
2018-03-12 AUSTRIA Vienna Embedded Systems Software Development (2 days) 1500 EUR  18 
2018-03-12 RUSSIA Moscow Designing with VHDL (3 days) 72900 RUB  15 
2018-03-13 AUSTRIA Vienna Embedded Systems Design (2 days) 1500 EUR  18 
2018-03-14 NETHERLANDS Heesch DSP Design Using System Generator (2 days) 1450 EUR  18 
2018-03-15 RUSSIA Moscow Designing FPGAs Using the Vivado Design Suite 4 (3 days) 72900 RUB  15 
2018-03-19 NETHERLANDS Heesch Embedded Systems Design (2 days) 1450 EUR  18 
2018-03-19 AUSTRIA Vienna Embedded Open-Source Linux Development (3 days) 2250 EUR  27 
2018-03-21 CO Longmont Zynq UltraScale+ MPSoC for the System Architect (2 days) 1400 USD  14 
2018-03-21 NETHERLANDS Heesch Embedded Systems Software Design (2 days) 1450 EUR  18 
2018-03-22 AUSTRIA Vienna Custom (2 days) 1500 EUR  18 
2018-03-22 RUSSIA Moscow Advanced VHDL (2 days) 48900 RUB  10 
2018-03-26 AUSTRIA Vienna Designing with Multi-Gigabit Serial I/O (3 days) 2250 EUR  27 
2018-03-26 RUSSIA Moscow Designing with Multi-Gigabit Serial I/O (3 days) 72900 RUB  15 
2018-03-26 NY - ROCHESTER Rochester Vivado Boot Camp Phase-3 Custom (3 days) 3000 USD  30 
2018-03-27 AUSTRIA Vienna Designing with UltraScale FPGA Transceivers (2 days) 1500 EUR  18 
2018-03-28 RUSSIA Moscow Embedded Systems Software Design (2 days) 48900 RUB  10 
2018-03-29 AUSTRIA Vienna Connectivity Memory Interfaces (2 days) 1500 EUR  18 
2018-03-29 AUSTRIA Vienna Custom (2 days) 1500 EUR  18 
2018-03-29 AUSTRIA Vienna Designing a LogiCORE PCI Express System (2 days) 1500 EUR  18 
2018-04-02 RUSSIA Moscow Partial Reconfiguration (2 days) 48900 RUB  10 
2018-04-03 NETHERLANDS Heesch Partial Reconfiguration (2 days) 1450 EUR  18 
2018-04-04 RUSSIA Moscow Designing with UltraScale FPGA Transceivers (2 days) 48900 RUB  10 
2018-04-04 AUSTRIA Vienna DSP Design Using System Generator (2 days) 1500 EUR  18 
2018-04-05 NETHERLANDS Heesch UltraFast Design Methodology (2 days) 1450 EUR  18 
2018-04-09 NETHERLANDS Heesch Doulos Comprehensive VHDL Custom (5 days) 3595 EUR  54 
2018-04-09 NETHERLANDS Heesch Doulos VHDL for FPGA Design Custom (3 days) 2495 EUR  38 
2018-04-10 AUSTRIA Vienna Designing with the UltraScale Architecture (2 days) 1500 EUR  18 
2018-04-10 AUSTRIA Vienna Designing with 7 Series (2 days) 1500 EUR  18 
2018-04-11 RUSSIA Moscow Designing with 7 Series (2 days) 48900 RUB  10 
2018-04-12 AUSTRIA Vienna Zynq-7000 All Programmable SoC (2 days) 1500 EUR  18 
2018-04-12 NETHERLANDS Heesch Doulos Advanced VHDL Custom (2 days) 1795 EUR  27 
2018-04-12 RUSSIA Moscow PCIe Protocol (1 day) 24900 RUB 
2018-04-16 RUSSIA Moscow Designing a LogiCORE PCI Express System (2 days) 48900 RUB  10 
2018-04-23 AUSTRIA Vienna Partial Reconfiguration (2 days) 1500 EUR  18 
2018-04-23 NETHERLANDS Heesch Designing with 7 Series (2 days) 1450 EUR  18 
2018-04-23 RUSSIA Moscow Designing with the UltraScale Architecture (2 days) 48900 RUB  10 
2018-04-25 RUSSIA Moscow Designing with Ethernet MAC Controllers (2 days) 48900 RUB  10 
2018-04-30 AUSTRIA Vienna Embedded Systems Software Development (2 days) 1500 EUR  18 
2018-04-30 NETHERLANDS Heesch Zynq-7000 All Programmable SoC (2 days) 1450 EUR  18 
2018-05-01 AUSTRIA Vienna Embedded Systems Design (2 days) 1500 EUR  18 
2018-05-07 AUSTRIA Vienna Embedded Open-Source Linux Development (3 days) 2250 EUR  27 
2018-05-10 AUSTRIA Vienna Custom (2 days) 1500 EUR  18 
2018-05-14 RUSSIA Moscow DSP Design Using System Generator (2 days) 48900 RUB  15 
2018-05-15 AUSTRIA Vienna Designing with UltraScale FPGA Transceivers (2 days) 1500 EUR  18 
2018-05-17 AUSTRIA Vienna Connectivity Memory Interfaces (2 days) 1500 EUR  18 
2018-05-17 AUSTRIA Vienna Custom (2 days) 1500 EUR  18 
2018-05-17 AUSTRIA Vienna Designing a LogiCORE PCI Express System (2 days) 1500 EUR  18 
2018-05-21 AUSTRIA Vienna Designing with Verilog (3 days) 2250 EUR  27 
2018-05-21 AUSTRIA Vienna Designing with Verilog (3 days) 2250 EUR  27 
2018-05-21 RUSSIA Moscow Embedded Design with PetaLinux Tools (2 days) 48900 RUB  10 
2018-05-22 AUSTRIA Vienna Designing with System Verilog (2 days) 1500 EUR  18 
2018-05-24 RUSSIA Moscow Designing with VHDL (3 days) 72900 RUB  15 
2018-05-24 AUSTRIA Vienna Advanced VHDL (2 days) 1500 EUR  18 
2018-05-24 AUSTRIA Vienna Verification with System Verilog (2 days) 1500 EUR  18 
2018-05-28 RUSSIA Moscow Zynq-7000 All Programmable SoC (2 days) 48900 RUB  10 
2018-05-30 AUSTRIA Vienna DSP Design Using System Generator (2 days) 1500 EUR  18 
2018-05-30 RUSSIA Moscow Designing with System Verilog (2 days) 48900 RUB  10 
2018-06-05 AUSTRIA Vienna Designing with 7 Series (2 days) 1500 EUR  18 
2018-06-05 AUSTRIA Vienna Designing with the UltraScale Architecture (2 days) 1500 EUR  18 
2018-06-06 RUSSIA Moscow Embedded Systems Design (2 days) 48900 RUB  10 
2018-06-07 AUSTRIA Vienna Zynq-7000 All Programmable SoC (2 days) 1500 EUR  18 
2018-06-11 AUSTRIA Vienna Partial Reconfiguration (2 days) 1500 EUR  18 
2018-06-13 RUSSIA Moscow Designing FPGAs Using the Vivado Design Suite 2 (3 days) 72900 RUB  15 
2018-06-18 AUSTRIA Vienna Embedded Systems Software Development (2 days) 1500 EUR  18 
2018-06-18 RUSSIA Moscow Designing with Multi-Gigabit Serial I/O (3 days) 72900 RUB  15 
2018-06-19 AUSTRIA Vienna Embedded Systems Design (2 days) 1500 EUR  18 
2018-06-25 RUSSIA Moscow Verification with System Verilog (2 days) 48900 RUB  10 
2018-06-25 AUSTRIA Vienna Embedded Open-Source Linux Development (3 days) 2250 EUR  27 
2018-06-27 RUSSIA Moscow Designing with UltraScale FPGA Transceivers (2 days) 48900 RUB  10 
2018-06-28 AUSTRIA Vienna Custom (2 days) 1500 EUR  18 
2018-07-02 AUSTRIA Vienna Designing with Multi-Gigabit Serial I/O (3 days) 2250 EUR  27 
2018-07-03 AUSTRIA Vienna Designing with UltraScale FPGA Transceivers (2 days) 1500 EUR  18 
2018-07-05 AUSTRIA Vienna Custom (2 days) 1500 EUR  18 
2018-07-05 AUSTRIA Vienna Designing a LogiCORE PCI Express System (2 days) 1500 EUR  18 
2018-07-05 AUSTRIA Vienna Connectivity Memory Interfaces (2 days) 1500 EUR  18 
2018-07-09 AUSTRIA Vienna Designing with Verilog (3 days) 2250 EUR  27 
2018-07-09 AUSTRIA Vienna Designing with Verilog (3 days) 2250 EUR  27 
2018-07-10 AUSTRIA Vienna Designing with System Verilog (2 days) 1500 EUR  18 
2018-07-12 AUSTRIA Vienna Verification with System Verilog (2 days) 1500 EUR  18 
2018-07-12 AUSTRIA Vienna Advanced VHDL (2 days) 1500 EUR  18 
2018-07-18 AUSTRIA Vienna DSP Design Using System Generator (2 days) 1500 EUR  18 
2018-07-20 AUSTRIA Vienna C-based HLS Coding for Software Designers (2 days) 750 EUR  18 
2018-07-24 AUSTRIA Vienna Designing with 7 Series (2 days) 1500 EUR  18 
2018-07-24 AUSTRIA Vienna Designing with the UltraScale Architecture (2 days) 1500 EUR  18 
2018-07-26 AUSTRIA Vienna Zynq-7000 All Programmable SoC (2 days) 1500 EUR  18 
2018-07-30 AUSTRIA Vienna Partial Reconfiguration (2 days) 1500 EUR  18 
2018-08-06 AUSTRIA Vienna Embedded Systems Software Development (2 days) 1500 EUR  18 
2018-08-07 AUSTRIA Vienna Embedded Systems Design (2 days) 1500 EUR  18 
2018-08-13 AUSTRIA Vienna Embedded Open-Source Linux Development (3 days) 2250 EUR  27 
2018-08-16 AUSTRIA Vienna Custom (2 days) 1500 EUR  18 
2018-08-20 AUSTRIA Vienna Designing with Multi-Gigabit Serial I/O (3 days) 2250 EUR  27 
2018-08-21 AUSTRIA Vienna Designing with UltraScale FPGA Transceivers (2 days) 1500 EUR  18 
2018-08-23 AUSTRIA Vienna Designing a LogiCORE PCI Express System (2 days) 1500 EUR  18 
2018-08-23 AUSTRIA Vienna Custom (2 days) 1500 EUR  18 
2018-08-23 AUSTRIA Vienna Connectivity Memory Interfaces (2 days) 1500 EUR  18 
2018-08-27 AUSTRIA Vienna Designing with Verilog (3 days) 2250 EUR  27 
2018-08-27 AUSTRIA Vienna Designing with Verilog (3 days) 2250 EUR  27 
2018-08-28 AUSTRIA Vienna Designing with System Verilog (2 days) 1500 EUR  18 
2018-08-30 AUSTRIA Vienna Verification with System Verilog (2 days) 1500 EUR  18 
2018-08-30 AUSTRIA Vienna Advanced VHDL (2 days) 1500 EUR  18 
2018-09-05 AUSTRIA Vienna DSP Design Using System Generator (2 days) 1500 EUR  18 
2018-09-11 AUSTRIA Vienna Designing with 7 Series (2 days) 1500 EUR  18 
2018-09-11 AUSTRIA Vienna Designing with the UltraScale Architecture (2 days) 1500 EUR  18 
2018-09-13 AUSTRIA Vienna Zynq-7000 All Programmable SoC (2 days) 1500 EUR  18 
2018-09-17 AUSTRIA Vienna Partial Reconfiguration (2 days) 1500 EUR  18 
2018-09-18 AUSTRIA Vienna Custom (3 days) 0 EUR  27 
2018-09-18 AUSTRIA Vienna Custom (3 days) 0 EUR  27 
2018-09-24 AUSTRIA Vienna Embedded Systems Software Development (2 days) 1500 EUR  18 
2018-09-25 AUSTRIA Vienna Embedded Systems Design (2 days) 1500 EUR  18 
2018-10-01 AUSTRIA Vienna Embedded Open-Source Linux Development (3 days) 2250 EUR  27 
2018-10-04 AUSTRIA Vienna Custom (2 days) 1500 EUR  18 
2018-10-08 AUSTRIA Vienna Designing with Multi-Gigabit Serial I/O (4 days) 2250 EUR  28 
2018-10-09 AUSTRIA Vienna Designing with UltraScale FPGA Transceivers (2 days) 1500 EUR  18 
2018-10-11 AUSTRIA Vienna Custom (2 days) 1500 EUR  18 
2018-10-11 AUSTRIA Vienna Designing a LogiCORE PCI Express System (2 days) 1500 EUR  18 
2018-10-11 AUSTRIA Vienna Connectivity Memory Interfaces (2 days) 1500 EUR  18 
2018-10-15 AUSTRIA Vienna Designing with Verilog (3 days) 2250 EUR  27 
2018-10-15 AUSTRIA Vienna Designing with Verilog (3 days) 2250 EUR  27 
2018-10-16 AUSTRIA Vienna Designing with System Verilog (2 days) 1500 EUR  18 
2018-10-18 AUSTRIA Vienna Verification with System Verilog (2 days) 1500 EUR  18 
2018-10-18 AUSTRIA Vienna Advanced VHDL (2 days) 1500 EUR  18 
2018-10-23 AUSTRIA Vienna DSP Design Using System Generator (2 days) 1500 EUR  18 
2018-10-30 AUSTRIA Vienna Designing with 7 Series (2 days) 1500 EUR  18 
2018-10-30 AUSTRIA Vienna Designing with the UltraScale Architecture (2 days) 1500 EUR  18 
2018-11-01 AUSTRIA Vienna Zynq-7000 All Programmable SoC (2 days) 1500 EUR  18 
2018-11-05 AUSTRIA Vienna Partial Reconfiguration (2 days) 2250 EUR  18 
2018-11-12 AUSTRIA Vienna Embedded Systems Software Development (2 days) 1500 EUR  18 
2018-11-13 AUSTRIA Vienna Embedded Systems Design (2 days) 1500 EUR  18 
2018-11-19 AUSTRIA Vienna Embedded Open-Source Linux Development (3 days) 2250 EUR  27 
2018-11-22 AUSTRIA Vienna Custom (2 days) 1500 EUR  18 
2018-11-26 AUSTRIA Vienna Designing with Multi-Gigabit Serial I/O (2 days) 2250 EUR  18 
2018-11-27 AUSTRIA Vienna Designing with UltraScale FPGA Transceivers (2 days) 1500 EUR  18 
2018-11-29 AUSTRIA Vienna Custom (2 days) 1500 EUR  18 
2018-11-29 AUSTRIA Vienna Designing a LogiCORE PCI Express System (2 days) 1500 EUR  18 
2018-11-29 AUSTRIA Vienna Connectivity Memory Interfaces (2 days) 0 EUR  18 
2018-12-03 AUSTRIA Vienna Designing with Verilog (3 days) 2250 EUR  27 
2018-12-03 AUSTRIA Vienna Designing with Verilog (3 days) 2250 EUR  27 
2018-12-04 AUSTRIA Vienna Designing with System Verilog (2 days) 1500 EUR  18 
2018-12-06 AUSTRIA Vienna Verification with System Verilog (2 days) 1500 EUR  18 
2018-12-06 AUSTRIA Vienna Advanced VHDL (2 days) 1500 EUR  18 
2018-12-12 AUSTRIA Vienna DSP Design Using System Generator (2 days) 1500 EUR  18 

 
/csi/footer.htm