Digital Communications Curriculum Resources

Related Information

Use System Generator for DSP and associated resources to develop labs covering fundamental and advanced digital signal processing courses.

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Access Application Notes
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Check out Interesting Research Projects

Access System Generator for DSP Resources

System Generator for DSP includes blocksets useful for digital communications labs. Some of these blocks are implemented in hardware as IP (Intellectual Property) cores generated from ISE Foundation's Core Generator for optimal results. Select IP Cores must be licensed. Refer to the System Generator User Guide for a complete description of each block.

System Generator for DSP also includes a set of free reference designs. The table below lists some example designs useful for digital communications.

Reference Designs
Product Name/Type	Description
16-QAM Demodulator	This design implements an equalized 16-QAM demodulator for use in a software defined radio. The receiver architecture provides subsystems that demonstrate adaptive channel equalization and carrier tracking on a random QAM data source.
A QAM System with packet framing and FEC for Telemetry Channels	This design implements a QAM system with packet framing and FEC for telemetry channels. The system is implemented according to the specifications provided by the Consultative Committee for Space Data Systems for telemetry channel coding specification (CCSDS 101.0-B-5).
Concatenated FEC codec for DVB Standard	This design demonstrates a concatenated forward error correction scheme using the blocks provided in the Xilinx Communication library. The scheme is implemented according to the specifications provided in the European Telecommunication Standard (ETS 300 421) for Digital Video Broadcasting.
Costas Loop Carier Recovery
MIMO Channel Model Simulation	This design demonstrates a Multiple Input-Multiple Output (MIMO) channel model. The model parameters are based on four element linear transmit and receive arrays with flat fading. The output scope shows the time domain channel response (real, imaginary, magnitude and phase).
SISO Channel Model Simulation	This design demonstrates a Single Input-Single Output (SISO) channel model. The model parameters are obtained from 3GPP Technical Specification 25.104 Annex B.2, multi-path fading propagation conditions (Case 4). The output scope shows the channel response. Notice that the channel exhibits both fast and slow fading.
Digital down converter for GSM	Virtually all digital receivers perform channel access using a digital down-converter (DDC). The desired channel is translated to baseband using the digital mixer comprised of multipliers, M1 and M2, and a direct digital synthesizer (DDS). The sample rate of the signal is then adjusted to match the channel bandwidth. This is performed using a multi-stage multi-rate filter consisting of a CIC Filter and two polyphase decimators. The functions performed in the system are waveform synthesis (DDS), complex multiplication, and multirate filtering. The overall sample rate change of the DDC is 192. The DDS mixer signal has a spurious free dynamic range (SFDR) of 102dB. The data rate can support up to 165 MSPS and is limited by the performance of the DDS Mixer.

Access useful Xilinx Application Notes

Xilinx application notes cover topics ranging from FPGA resource usage to application examples. The links
below provide direct access to application notes for supported XUP board device families

Access Teaching Materials

Access text books and materials for teaching courses using Xilinx.

DSP: Designing for Optimal Results online book
DSP Primer lecture notes and lab exercises targeting the XUP Virtex-II Pro

Download Course Materials

Listed below are Universities that post lecture notes and/or lab exercises on their course websites
to share with the academic community.

Links to Academic Partner Digital Logic Teaching Materials
University	Course Name/Number
Rice University	ELEC433:Digital Communications Laboratory

Interesting Research Projects

Learn how Universities are using the latest Xilinx technology in research.

WARP Wireless Access Research Platform developed by Rice University