DSP Primer Workshop

Introduction

The DSP Primer workshop was designed to enable academics to teach FPGA-based DSP architecture courses and implement research projects targeting Xilinx FPGAs. The workshop lecture and lab materials cover a wide range of theoretical DSP topics and go in depth into how such algorithms can be implemented in the latest Xilinx FPGA technology using System Generator for DSP. System Generator for DSP is a Xilinx blockset for Simulink® (The Mathworks, Inc.) that enable engineers to model and create complex DSP systems, and generate HDL code targeting the industry’s most advanced FPGAs.

The intensive lab exercises give academics the experience they need to learn the software flow from algorithm design to hardware implementation targeting the XUP Virtex®-II Pro board. Academics will learn how to create FPGA-based DSP designs utilizing the audio capabilities of the board to illustrate topics taught in fundamental and advanced DSP.

 

Teach with Quality Lecture Materials

• When to use an FPGA or DSP processor - or both
• Arithmetic issues - How to implement adds, multiplies, and more
• Dealing with overflow and underflow scenarios
• Efficient FIR filter design and implementation
• The use of IIR filters in DSP for FPGA applications
• Adaptive Filtering in FPGAs

Figure 1

Learn a wide variety of theoretical DSP topics with the lecture notes

 

Administer Lab Exercises

• Simple Arithmetic
• FIR Filtering
• Adaptive Filtering
• Low-Pass Cascaded CIC Filters
• Digital Down Conversion
• Numerically Controlled Oscillators
• CORDIC - vector magnitude calculations

Figure 2

Reinforce the knowledge taught in the lecture using the extensive set of labs

 

Create DSP Designs with System Generator for DSP

• Basic elements
• Communication building blocks
• Control logic
• DSP building blocks
• Math functions
• Memory blocks
• And more

Figure 3

Learn to create FPGA-based DSP algorithms using System Generator for DSP

 

Verify Design in Hardware targeting the XUP Virtex-II Pro

• Virtex-II Pro xc2vp30 FPGA
• Audio CODEC
• Line In/Out audio connectors

 

Figure 4

Realize your algorithms in hardware using Xilinx University Program boards

About the Author

Professor Bob Stewart, University of Strathclyde, has been working in DSP and digital communications for the last 20 years.  His current position is as a Professor at the University of Strathclyde, Glasgow, Scotland in the Department of Electronic and Electrical Engineering.  Since 1997 he has also been a Visiting Professor at UCLA Extension, Los Angeles, USA, where he presents short courses on DSP and digital communications. In the early part of his career, Bob started work with Wolfson Microelectronics Ltd in Edinburgh in 1985, prior to starting a PhD degree in 1986 at the University of Strathclyde, before going on to study at University of Southern California, in Los Angeles, and then in 1990 taking a Visiting Faculty position at University of Minnesota, Minneapolis, USA.

Bob currently runs an active research group at Strathclyde, where the group actively uses Xilinx FPGAs for implementation of adaptive signal processing algorithms, digital communications standards implementations (802.20, 3G LTE), and low power DSP techniques for wireless sensor networks.  He has also worked extensively with industry and has consulted to a number of bluechip, as well as smaller, companies involved in DSP and digital communications.

He is also a past Chairman of the IET Signal Processing Professional Network, has held a Fellowship of Engineering Industrial Fellowship and will be Technical Chairman of the EUSIPCO conference in 2009.  He has been involved in and produced more than 120 publications in various aspects of DSP.