Product|gsd

   
Xilinx : Products and Services : Design & Education Services : Xilinx University Program : Professor Workshops : DSP Workshop
 
Digital Signal Processing Design Flow Workshop
The DSP Design Flow workshop provides an introduction to the advanced tools you need to design and implement DSP algorithms targeting FPGAs. This intermediate workshop focuses on learning how to use System Generator for DSP software. Through hands-on exercises, you will implement a design from algorithm concept to verification in hardware. 
 
Workshop Overview  
  • Level: Intermediate
  • Workshop Duration: 2 Days
  • Prerequisits:
    • Fundamentals of MATLAB/Simulink and Xilinx FPGAs
    • Basics of digital signal processing theory for functions such as FIR (Finite Impulse Response) filters.
    • Basic digital design experience
  • Workshop Goals:
    • Learn how to implement a DSP design without having to be an FPGA expert.
    • Become comfortable using System Generator to develop lectures and labs, or implement research.
  • Skills Gained:
    • Gain a basic introduction to the Simulink tools
    • Become familiar with the Xilinx blockset for Simulink
    • Learn how to create basic fixed-point DSP designs using the Xilinx blockset
    • Perform hardware-in-the-loop verification on a hardware target
Agenda  

 

  • Day 1: 9am-5pm (DSP Design Implementation Tools)
    • Introduction to FPGAs for DSP
    • Introduction to System Generator
    • Simulink Basics
    • Lab 1: Using Simulink
    • Basic Xilinx Design Capture
    • Lab 2: Getting Started with Xilinx System Generator
    • Signal Routing
    • Lab 3: Signal Routing

     

  • Day 2: 9am-5pm (Digital Signal Processing Functions)
    • Implementing System Control
    • Lab 4: Implementing System Control
    • Multi-Rate Systems
    • Lab 5: Designing a MAC-Based FIR
    • Filter Design
    • Lab 6: Designing a FIR Filter using the DA FIR block
Lab Description  

    • Lab 1: Get familiar with some of the basic Simulink blocks

    • Lab 2 : Create a 12x8 MAC using the System Generator blockset, which will be used in lab 5 to create a MAC-based FIR filter

    • Lab 3: Create padding and unpadding logic that will be used in lab 5 for reading/writing data to a dual-port block RAM, which will serve as data/coefficient storage for the MAC-based FIR filter.

    • Lab 4: Create an address generator using 1) basic System Generator blocks, and 2) m-code block. The address generator will be used in lab 5 to address a dual-port block memory that contains data/coefficients.

    • Lab 5: You will create a 92-tap MAC based FIR filter; you will simulate the filter with white noise and verify in hardware via JTAG co-simulation

    • Lab 6: Use the FDA Tool to generate coefficients for a low-pass filter; implement low-pass filter using DA FIR filter block from System Generator; simulate with white noise and test in hardware via JTAG co-simulation
Workshop Slides and Laboratory Exercises
 

 

 
/csi/footer.htm