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Xilinx : Xilinx University Program :Professor Workshops : FPGA Design Flow
 
FPGA Design Flow Workshop
This course provides Professors with an introduction to designing with Xilinx FPGAs using ISE development software tools. 
 
Workshop Overview  
  • Level: Introductory
  • Workshop Duration: 2 Days
  • Who should attend? Professors who are new to FPGAs or Xilinx technology and wish to develop basic labs in Digital Design.
  • Prerequisites:
    • Digital Design Experience
    • Basic HDL Knowledge (VHDL or Verilog)
    • Understanding of 8-bit controllers

    •  

  • Skills Gained: After completing this training, attendees will be able to:
    • Describe the general FPGA architectures and the design flow
    • Use the Architecture Wizard to configure architecture features such as the DCM
    • Enter global timing constraints to communicate timing objectives to ISE
    • Understand the basics of the PicoBlaze 8-bit controller
    • Pinpoint design bottlenecks using the reports
    • Understand how different synthesis options can impact performance
    • Understand the various implementation options
    • Create and integrate cores into your design flow using the Core Generator
    • Use Chipscope-Pro to perform on-chip verification

Agenda  

 

  • Day 1: 9am-5pm (Architectures and ISE Flow)
    • Basic FPGA Architecture
    • Xilinx Tool Flow
    • Lab 1: Xilinx tool flow
    • Architecture Wizard and PACE                                         
    • Lab 2: Architecture Wizard and PACE
    • Reading Reports
    • Global Timing Constraints
    • Lab 3: Global Timing Constraints
    • FPGA Design Techniques

     

  • Day 2: 9am-5pm (Design intro and Verification)
    • Synchronous Design Techniques
    • Floorplanner
    • Synthesis Techniques
    • Lab 4: Synthesis Techniques
    • Implementation Options
    • Core Generator System
    • Lab 5: Core Generator System
    • Chipscope-Pro
    • Lab 6: Chipscope-Pro


Workshop Slides and Laboratory Exercises

 
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