XUPV2P Demonstration
Design
This demonstration design uses the AC 97 audio codec as the audio A/D and D/A to the Xilinx XC2VP30 FPGA, for capturing audio to be filtered and played back to the user's speakers. The filtered or unfiltered digital audio data is presented to a 64 point FFT to convert the time domain audio, to frequency domain spectral information. The output of the FFT is sampled and displayed graphically using character mapped graphics to an 800 X 600 pixel VGA resolution display using Fairchild FMS3818 D/A to take the digital data from the FPGA to the SVGA analog output.
|
28.7 MB |
Video Decoder
using VDEC-1
The XUPV2P Development System when equipped with a VDEC1 Video decoder uses an Analog Devices ADV7183B to sample the incoming analog video and convert it to digital values according to the video standards ITU-R.656 and ITU-R BT.601. In this example design, the video is then further converted to be displayed on a standard VGA display as progressive video output on the XUP board’s SVGA port. |
246 kB |
Slide Show
using 256 MB DDR Memory
This design reads binary graphic data (.bmp)
stored on a compact flash and presents it on an external display
monitor. It uses the System Ace controller to read data from
compact flash into memory, on 2 MB boundaries. The memory controller
is setup for a 256 MB Dimm. By moving the VGA display pointer,
the data is presented like a slide slow through the XSGA port
from the FPGA to the SVGA analog output. |
2.9 MB |
Ethernet
MAC OneWire
This design implements a web server running on the XUP-V2Pro Development System, with a OneWire core. The WEB server will display the user DIP switches and control the LEDs from your browser. The core uses the silicon serial number as an ethernet MAC address, although the serial number is unique for all the boards, it is not a registered MAC address. |
547 kB |
OneWire
This design implements a a OneWire core. The
core reads the silicon serial number and displays it on the
terminal window through a UART. |
148 kB |
PS2
This design implements a core which reads in
the characters typed in on a keyboard connected to either of
the two PS2 ports and displays it on the terminal window through
a UART. |
170 kB |
Edge Detection
This design shows how a 2-D Image filter can
be efficiently realised using n-tap MAC FIR Filters. The filters
used in teh '5x5 Filter' subsystem are from the Custom FIR library
provided as a System Generator For DSP demo. The sysgenConv5x5_hw_in_lup.mdl
example uses the XUPV2P Development System as a hardware accelerator
to decrease simulation time. |
72 kB |
256 MB Single
Rank DDR Memory with VGA Controller
|
435 kB |
| 512 MB Dual
Rank DDR Memory with VGA Controller |
414 kB |
512 MB Single
Rank DDR Memory with VGA Controller
|
341 kB |