Base System Builder & Reference Design Material |
The Xilinx Base System Builder (BSB) wizard helps users quickly build a working embedded processing system design through an easy to use GUI interface. The XPS project created by BSB can be run as generated or further enhanced with peripherals added from the Embedded Development Kit (EDK) IP catalog.
 Master UCF Pin Constraints
EDK Reference Designs
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Memory Interface Generator Design |
Using the Xilinx Core Generator™ Memory Interface Generator to build a DDR2 design.
 MIG Design Creation
 MIG Design zip
MIG Design Overlay zip
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Aurora Design |
| This reference design and tutorial demonstrates a 2 byte, single lane GTP Aurora design.
Aurora SMA Design Creation
Aurora Design
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IBERT Design |
| This design contains a tutorial demonstrating how to generate an IBERT design that exercises the GTP transceivers using the ChipScope™ Pro Serial IO Toolkit.
IBERT SATA GTP Design Creation
IBERT Design
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PCIe x1 Endpoint Design |
A Xilinx CORE Generator™ design is shown that leverages both the hardened PCIe Endpoint Block and a high-performance RocketIO GTP transceiver to create a single-lane PCI Express x1 Endpoint.
PCIe x1 Endpoint Design Creation
PCIe x1 Endpoint Design
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Configuration Methods |
| The board may be used to demonstrate a variety of Virtex-5 configuration methods. Initial board bring-up and testing can be accomplished with the Xilinx tools, a JTAG cable, along with the bitstreams and ELF files from the reference designs. Subsequently, ACE files containing both hardware and software initialization components can be generated and loaded from a CompactFlash card by the onboard System ACE™ CF controller. A new Virtex-5 configuration method loads bitstreams directly from a linear flash memory device. Demonstrating the various Virtex-5 configuration methods is user-selectable through a DIP switch.
Flash Images
CPLD Programming File
CPLD Design Files
IDT5V9885 Clock Setup File
USB EEPROM Programming File
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