Product|devboards
 

Home : Products & Services : Xilinx University Program : XUPV5-LX110T Development System : XUPV5-LX10T Reference Designs

XUPV5-LX110T Reference Designs

 
Product Details
Base System Builder & Reference Design Material
The Xilinx Base System Builder (BSB) wizard helps users quickly build a working embedded processing system design through an easy to use GUI interface. The XPS project created by BSB can be run as generated or further enhanced with peripherals added from the Embedded Development Kit (EDK) IP catalog.
 Master UCF Pin Constraints

EDK Reference Designs
Memory Interface Generator Design

Using the Xilinx Core Generator™ Memory Interface Generator to build a DDR2 design.

pdf  MIG Design Creation
  MIG Design zip
  MIG Design Overlay zip

Aurora Design

This reference design and tutorial demonstrates a 2 byte, single lane GTP Aurora design.

pdf  Aurora SMA Design Creation
 Aurora Design

IBERT Design

This design contains a tutorial demonstrating how to generate an IBERT design that exercises the GTP transceivers using the ChipScope™ Pro Serial IO Toolkit.

pdf  IBERT SATA GTP Design Creation
 IBERT Design

PCIe x1 Endpoint Design

A Xilinx CORE Generator™ design is shown that leverages both the hardened PCIe Endpoint Block and a high-performance RocketIO GTP transceiver to create a single-lane PCI Express x1 Endpoint.

pdf  PCIe x1 Endpoint Design Creation
zip  PCIe x1 Endpoint Design

Configuration Methods

The board may be used to demonstrate a variety of Virtex-5 configuration methods. Initial board bring-up and testing can be accomplished with the Xilinx tools, a JTAG cable, along with the bitstreams and ELF files from the reference designs. Subsequently, ACE files containing both hardware and software initialization components can be generated and loaded from a CompactFlash card by the onboard System ACE™ CF controller. A new Virtex-5 configuration method loads bitstreams directly from a linear flash memory device. Demonstrating the various Virtex-5 configuration methods is user-selectable through a DIP switch.

zip  Flash Images
zip CPLD Programming File
zip CPLD Design Files
zip IDT5V9885 Clock Setup File
zip USB EEPROM Programming File

 
User Manual
Reference Designs
Ordering Information
/csi/footer.htm