High-Level Synthesis

Advanced algorithms used today in wireless, medical, defense, and consumer applications are more sophisticated than ever before. This complexity combined with aggressive development and verification schedules challenges even the most experienced RTL teams. High-Level Synthesis accelerates design implementation by enabling C, C++ and SystemC specifications to be directly targeted into FPGAs without the need to manually create RTL. This provides system and design architects alike with a faster and more robust way of delivering quality designs.

HLS or Vivado HLS Standalone?

Simply put, if you are targeting Series-7 or later family devices and have installed Vivado/ISE System Edition, you should already have a license to use HLS feature. In case the target family device is Spartan-6 or earlier, you require to use Vivado HLS Standalone with ISE tools. The Vivado HLS Standalone feature requires a separate license file.

Request Donation

Professors who can justify the need of using the tools may request a donation. Please fill out the request form for donation consideration. The outcome may result in either donation of license(s) or recommendation to use an evaluation license. Qualification criteria include the completeness of the form, clarity of the proposed project description, the extent of technology usage, and the extent of High-Level Synthesis experience. Your request should demonstrate critical need for using this tool.

Only professors and researchers may submit the survey form.

The response time for initial evaluation after submitting the form may be around two weeks.