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High-Level Synthesis using Vivado HLS

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Vivado HLS Licensing
Vivado HLS tool is a separate product, not bundled within ISE Design Suite. Minimum of Embedded Design Suite is required to complete these labs. Learn more on the requirements and procedure in obtaining a license.
Course Description This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems using Vivado HLS specifically targeting Zynq. 
Level Intermediate
Training Duration 2 days
Who Should Attend Professors who are familiar with Xilinx FPGA technology and wish to get up to speed with system design using high-level synthesis technique in Zynq.
Prerequisites
  • System level design experience using Xilinx FPGA
  • Basic experience with Xilinx ISE® Foundation™ and EDK software
  • Good understanding of C programming
Skills Gained

After completing this training, you will be able to:

  • Understand high-level synthesis flow of Vivado HLS
  • Apply directives to optimize design performance
  • Create a custom peripheral and add it to Zynq processing system
Course Overview

Day 1

  • Introduction to HLS with Vivado HLS
  • Using Vivado HLS
  • Lab 1: Creating Project and Understanding Reports
    • Experience a basic design flow of Vivado HLS and review generated output. Use Control Data Flow Graph (CDFG) to understand how the design is synthesized
  • Improving Performance
  • Lab 2: Optimizing Performance through Pipelining
    • Use pipelining technique to improve performance.
  • Data Types

Day 2

  • Optimizing for Area and Resources
  • Lab 3: Optimizing Area
    • Use directives to optimize resource sharing.
  • Handling Block and Port Level Protocols
  • Coding Style
  • Creating a Processor System using Zynq
  • Lab 4: Designing an Audio System
    • Use pcore generation capability of Vivado HLS and integrate generated pcore in an embedded system using ZedBoard.
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