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58G PAM4 Transceiver Performance

This demonstration showcases the latest in Xilinx SERDES development with the first public display of the Xilinx 58Gb/s PAM4 transceiver. The test chip implements full transmit and receive data paths with pattern generators and checkers. This demonstration shows both the high fidelity of the transmitter via an eye diagram and the strength of the receiver as data is run from another transmit lane, over a backplane and into the receiver to be equalized and received with orders of magnitude better BER than required.