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ar32375.zip
                           8 Kb  Uploaded: 04-08-2009
			        The MIG v2.3/v3.0 QDRII Virtex-5 design has the
			        potential to not complete calibration at
			        frequencies below 250MHz. See Xilinx Answer
			        32375 for details. The file attached includes
			        the work around and should be used until MIG 3.1
			        is available.
				Solution #: 32375
				For All Platforms
				SW Release: All
ar32375.zip
                           8 Kb  Uploaded: 04-08-2009
			        The MIG v2.3/v3.0 QDRII Virtex-5 design has the
			        potential to not complete calibration at
			        frequencies below 250MHz. See Xilinx Answer
			        32375 for details. The file attached includes
			        the work around and should be used until MIG 3.1
			        is available.
				Solution #: 32375
				For All Platforms
				SW Release: All
31974.zip
                          48 Kb  Uploaded: 04-02-2009
			        This is the design files that will enable EDK to
			        read and write to the Platform Flash XL using
			        the XPS_EMC core with updated XIL_FLASH
			        libraries.
				Solution #: 31794
				For All Platforms
				SW Release: 10.1
				Category: Utility, FPGA