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Programmable Chip Rate Solutions for 3G UMTS

Xilinx Design Services can provide a complete 3G UMTS 64 Channel Chip Rate Processing solution within a single FPGA. The solution below implements both Uplink and Downlink functions. These functions can be partitioned into separate devices if this is the preferred architecture.

Downlink The Downlink functionality can be achieved within a single XC2V1000 FPGA. This not only supports Transmit Diversity, STTD encoding, and compressed mode, it has the added value of performing the inner loop power control functions.
	Compliant to 3GPP specifications
	64 DCH channels supporting data rates up to 384K
	Up to 60 common channels allows multi-sector support
	Transmit diversity
	STTD encoding
	Separate weights per user per field per mode
	Compressed Mode support
	TPC insertion
	Inner loop power control
	Embedding processing reduces the system processing overhead
	Up to 16 antennae can be supported by the combiner
	AICH generation avoids interrupt latency issues
	Embedded SCH generation prioritization
Uplink The Uplink solution is customer dependent. This gives you the flexibility of being able to fully define the systems to your requirements while still keeping the benefits of fast time to market and low risk design flow. By using soft partitioning to remove the overhead on the processing and DSP functions, this solution also reduces the overall system complexity.
RACH Detection
	Detects all signatures
	Impact of cell size can be easily defined
	Detects preamble in all slots
	Full 4096 chip correlation
	Multiple Antennae can be supported
	Post processing of results available
Searcher
	Programmable search length
	Programmable search Window
	Coherent correlation length can be defined
	Non-coherent accumulation of correlated results across frame
	Embedded scheduler allows prioritization
	Post processing of results available
Rake Receiver
	Each finger can be allocated on a per user, per antenna basis
	Supports data rates up to 384K
	Can perform RACH message or DCH decoding
	System partitioning allows flexibility in Channel Estimation algorithm
	Tracking
	Control Symbol Extraction
	SIR measurement
	Inner loop power control support
	Compressed Mode support

Programmable Chip Rate Solutions for 3G UMTS Function Users Bits Window Length Slices Block RAMs Max Clock Frequency Example Xilinx Device Downlink 64 16 n/a n/a 3000 15 122.88MHz XC2V1000-4 RACH Preamble Detection n/a 6 512 Chips 4096 2000 18 122.88MHz XC2V1000-4 Searcher 64 7 256 Chips 10ms 4000 26 122.88MHz XC2V1000-4 Rake Receiver 256 (Fingers) 8 n/a n/a 4000 32 122.88MHz XC2V1000-4

Find Out For Yourself To find out more, email us at: designservices@xilinx.com