Editor’s Note: This content is contributed by Cindy Lee, Product Marketing manager at Xilinx
Massive growth in data traffic driven by cloud services and the rollout of 5G is creating challenges to keep up with burgeoning bandwidth requirements within networks. Line card port densities in routers and switches, optical standard evolution, and optical network bandwidth updates are major constraints to cost effectively keep pace with bandwidth needs. The transition to 58G transceivers is an important step to deliver 400G+data rates on the same existing footprint.
Evolution to PAM4 Signaling
<Figure 1. FPGA Transceiver Rates by Year>
NRZ (non-return-to-zero) has been the standardized encoding scheme for 25Gb/s. Yet demand for ever increasing capacity, long reach applications, and data rates continues. Data rates for high-speed interconnect with traditional NRZ signaling has hit a ceiling of about 25Gb/s data rate. PAM4 (4-level Pulse Amplitude Modulation) has been widely recognized as the most robust and scalable signaling standard for data rates above 25Gb/s.
With NRZ, you can transmit one bit of information (1 or 0) per clock period at a given frequency. Compared to NRZ, PAM4 cuts the bandwidth for a given data rate in half by transmitting twice more bits in each symbol. This allows users to double the bit rate in the channel without doubling the required bandwidth.
While the 28Gb/s bit rate is transmitted at 28Gbaud/s and has a Nyquist frequency of 14GHz with NRZ signaling, A 56Gb/s bit rate is transmitted at 28Gbaud/s and has a Nyquist frequency of 14GHz with PAM4 signaling. See Figure 2.
<Figure 2. PAM4 on Backplanes - Re-use Existing Materials and Platforms>
Advantages of PAM4
One challenge for systems providers is that their legacy backplanes and electrical interconnects cannot tolerate line rates beyond 25Gb/s. Another challenge is COTS of the whole set of materials, connectors, backplanes in the existing infrastructure. Because of the potent DSP-based equalization in the Virtex® UltraScale+™ FPGA’s GTM transceiver and the fact that channel losses will be similar to 25G line rates, existing 25G backplanes and cabling can be re-purposed as 56G media. The GTM transceiver can leverage that same material set while doubling the bandwidth. And Xilinx has been testing with a wide range of cables and backplanes to ensure any design will work when the Xilinx FPGA user moves to next-gen platforms and high-performance interconnects.
Xilinx Demonstrates 58G Capable GTM Transceivers with 100G Ethernet on Two Lanes
In this video, Xilinx demonstrates 100G Ethernet on two lanes via Xilinx’s 58G capable GTM transceivers and the Virtex® UltraScale+™ FPGA’s integrated 100G Ethernet subsystem. This video provides an overview of how GTM transceivers enable legacy hardware to support 58G PAM4.
Combining proven high-end Virtex UltraScale+ FPGA and fully compliant PAM4 technology, Virtex UltraScale+ 58G capable FPGAs are engineered for Data Center and Networking. Next generation modulation is coming. Xilinx gives our customers time to prepare for the next-gen platforms while preserving existing legacy infrastructure. Are you ready for prime time?
For more information, visit www.xilinx.com/58G.
Original Date: 02-14-2019