Editor’s Note: This content is contributed by Martin Gilpatric, Xilinx Technical Marketing - Transceivers
DesignCon 2019 has come and gone, and with it came a flurry of new interconnects targeting a variety of forward-looking serial technology. Xilinx partnered with four connector vendors to present six demonstrations showing what architects can look forward to using in their designs. From the near term 32G PCIe® style and emerging 58Gb/s PAM4 long reach interconnects to tomorrow’s 112G PAM4 topologies, Xilinx had SerDes technologies on display to fit everyone’s next generation wish list. In the following two weeks, we are going to release a series of Xilinx PAM4 technology demos from DesignCon. Stay tuned!
Direct Attach Copper (DAC) is a less expensive and lower power alternative to point-to-point optical interconnects since it is a passive connection, bypassing the retimers and optical circuitry that would otherwise be required. Luxshare provided a 1m DAC cable in an OSFP form factor across which Xilinx ran 112G PAM4 PRBS-31 data, provided by our 112G PAM4 test chip. This is a long channel to be running at such a high Nyquist, but we were still able to recover the data with an approximate 1e-6 pre-FEC BER, showing the capabilities of both the Luxshare interconnect and Xilinx transceiver technology.
Xilinx worked with Molex on a pair of demos that appeared in the Molex booth, both of which featured bleeding-edge PAM4 SerDes developed by Xilinx.
The GTM transceiver found in the Virtex® UltraScale+™ 58G PAM4 FPGAs was front and center, showing how 400G can be implemented using only copper. The channel provided by Molex consisted of a combination of their NearStack high-speed connectivity solution that bridges between the SMAs and the QSFP-DD cage, and a 3m, 28AWG QSFP-DD Direct Attach Copper cable. This is a highly flexible interconnect solution and results in only about 30dB of insertion loss. Even after that loss, the GTM transceiver recovered the data with an approximate pre-FEC BER of 1e-8, which becomes better than 1e-16 post-FEC.
The 112G PAM4 demonstration in the Molex booth featured the 112G PAM4 test chip developed by Xilinx. The channel provided by Molex was a real, honest, midplane—something that many considered impossible to implement at these rates. With losses near 30dB, this represents a realistic channel, and the ADC based receiver in the 112G PAM4 test chip recovered the data for a better than 1e-7 pre-FEC BER. 112G PAM4 is slated to join the Xilinx transceiver line up in Xilinx’s Versal™ ACAP devices.