December 20, 2021
Editor's Note: This content is contributed by Mike Thompson, Sr. Product LIne Manger for Versal Premium & HBM ACAPs, Virtex UltraScale+ FPGAs at Xilinx
Many industries continuously demand higher bandwidth capacities than today's technologies and form factors can support. The demand is for a more efficient, pervasive computing platform that scales beyond what CPU and GPU technologies can reach.
The Versal® Premium series was built for the most bandwidth and processing-intensive applications from cloud to core and metro network. This highly integrated Versal Premium series allows users to focus on implementing their unique core competencies and novel algorithms rather than designing connectivity and memory infrastructure to achieve the earliest possible time to market.
We hit an exciting milestone in April’21, as we announced first customer shipments for the Versal Premium series. Meanwhile, Versal Premium devices have gone through an exhaustive verification and characterization cycle. I am happy to say that we witnessed all major blocks were up and running within just a few days of first power on. This is a very fast bring-up. Nominally, getting to that state can take weeks or months!
In this blog, I want to highlight a couple of key features we showcased at OFC 2021 and share links to demo videos that highlight those features.
Versal Premium series implements 112G PAM4 transceivers, which are an evolution of our 58G PAM4 transceiver from 16nm Virtex® UltraScale+™ FPGAs, and our 32G NRZ transceivers, which have been working like a charm for several generations. You can see the excellent signal quality in this 112G SerDes demo, both transmit and recovered receive eyes look really good.
We’ve also brought up 600G Ethernet cores, or DCMACs, with built-in forward error correction (FEC). These 600G Ethernet cores can run all the standardized rates from 400G down to 100GE. And we can support rates beyond 400GE, like 800GE with Flex Ethernet. Rates from 100G down to 10G are supported with our 100G Multi-Rate Ethernet MAC (MRMAC). These cores are very modular, so, in your designs, you can choose to freely implement any combination of the PMA, PCS, MAC, or FEC as you see fit—all while uniquely retaining full access to the physical layer.
The integrated block for PCIe® is one of the data highways into a Versal Premium ACAP, addressing a wide range of functional and bandwidth needs. As PCIe Gen5 CPUs have started hitting the market this year, we’ve brought up PCIeGen5 with various test equipment. This video shows an 8-lane link at 32Gb/s per lane by the CPM.
Network security and high-speed encryption are an essential part of many applications now, and the High-Speed Crypto (HSC) Engines in the Versal Premium ACAP are a powerful, yet simple to implement, tool to help meet those cryptographic needs. With the HSC, it’s easy to achieve up to 1.6Tb/s of line-rate crypto in your design. We exercised the HSC Engines with what’s known as a known answer test in the demo. The HSC is configured as a single 400G pipe and the device passed the test.
Versal Premium series is here and is alive and kicking. Versal Premium devices are sampling now. Don’t hesitate to contact local sales teams to secure devices to begin implementing your leading-edge applications.
I’m looking forward to engaging with you more as we bring the next generation of the highest bandwidth, most compute-intensive systems to market together!