June 24, 2022
Editor’s Note: This content is republished from the MicroZed Chronicles, with permission from the author.
I am very interested in higher levels of abstraction for developing FPGAs and especially algorithms like image processing and control. Readers of my blog will know that HLS is a common topic in my articles, projects, and webinars.
As we know, HLS is a great entry point for accelerating FPGA designs. In addition, when we work with SoCs, we can also utilize the accelerated flow and OpenCL. We have examined this in past blogs and webinars as well.
The Vitis Model Composer flow is one higher level of abstraction tool that we have not yet examined. If you are not familiar with it, the Vitis Model Composer allows us to work with the MathWorks MATLAB and Simulink environment and enable developers to accelerate DSP, RF (think RFSoC), and Image processing.
Having recently purchased MATLAB and Simulink for another project, I thought it would be beneficial to take a look at Model Composer. One of the main advantages of Model Composer that is similar to Vitis HLS and the Vitis Acceleration flow is that you don’t need any previous experience with RTL design to effectively use it.
To get started, first we need to purchase an AMD-Xilinx Model Composer license. We also need MATLAB and Simulink licenses and we might need additional tool boxes depending on the application being developed.
Now let’s start at the beginning. Model Composer provides the developer with approximately 200 blocks that can be used in the Simulink environment. These models are composed of HDL, HLS, and AI Engine blocks (AI Engine development requires a Linux machine).
These blocks provide a range of functionality from ports and interfacing to mathematical operations in addition to linear algebra, data conversions, and signal processing. Along with composing the design in Simulink, we are also able to analyze the performance and deploy and test hardware in the loop.
One of the things I was keen to understand was the difference between the HDL and HLS block sets since both result in a IP block that we can deploy in our FPGA, typically via Vivado IP Integrator. As I understand it, the HDL blocks generate either a HDL netlist, Vivado IP block, synthesis checkpoint or co-simulation element. The HLS block set provides either a IP catalog component or a C++ file set that can be used in Vitis HLS and, of course, further optimized in Vitis HLS for the deployed target.
I am really interested to see the different approach between Model Composer and HLS flows. I’m also very interested in trying out the hardware in the loop verification which could be very powerful for some of the systems we develop.
Just like the first blog in the series from 2013, I am going to be learning how to use Model Composer as I create the blogs and material. I am looking forward to experimenting with it in addition to the tool chain to determine what impact it can have on the FPGA solutions we develop.