July 29, 2022
Editor’s Note: This content is republished from the MicroZed Chronicles, with permission from the author.
I have recently come across an interesting requirement from a customer that includes driving high-energy systems with a series of pulses that need to be able to be delayed with respect to each other in order to gain optimal performance.
This project is based upon a Kria SOM and I implemented the required functionality using the SelectIO resources available in the UltraScale architecture. Previously, we’ve looked at the 7 Series SelectIO resources (IDelay2/ODelay2 and SelectIO) so it’s appropriate that we also look at the UltraScale+ SelectIO resources.
Just like with 7 Series devices, there are a number of IO bank types on UltraScale architecture. These include the following:
We have a mix of HDIO and HPIO when we are working with the Zynq UltraScale+ MPSoC. This is the same for the device fitted to the Kria SOM.
Each of the HP or HR IO banks consist of 52 IO pins. Of these, 48 can be configured as either single ended or 24 differential pairs.
Internally, each of these banks is split into four-byte groups and each byte group is further split into two nibble groups. Two PLL and a MCMM are provided to support the advanced clocking needed for many applications.
Each of the nibbles contain a RX TX bitslice which is a change from the 7 Series devices.
The bitslice provides the ability to serialize and de-serialize, register, and delay input and output signals. On input signal, a small FIFO is also available for use.
In the documentation, using the bitslice is referred to as using the IO resources in the native mode. When we wish to use native mode IO resources in our FPGA designs, we should be using the high-speed IO wizard to ensure the desired configuration is viable. We can find the high-speed IO wizard in the IP library.
However, we might not want to use the SelectIO resources in the native mode but access the element of the bitslice. Just like with 7 Series devices, we can use the component primitives in this case. These include:
By using a combination of a variable length shift registers and the ODELAY3, I was able to implement a delay system for initial testing to see how the jitter performs on the board. Of course, the implementation required tight constraining to optimize the routing.
For comparison, the HD I/O supports a range of IO standards up to 250 Mb/s, HD I/O supports single ended standards, LVDS (with external termination), SSTL and HSTL. Within the HD I/O banks, there is no support for advanced IO features such as I/O SERDES, I/O Delay etc.
When it comes to achieving challenging timing IO relationships or implementing high-performance interfaces, the SelectIO resources of the UltraScale and UltraScale+ devices provide us with some interesting capabilities.