Experience adaptive acceleration – Edge to Cloud – in the Xilinx booth at Embedded World 2019.
Visit our booth to see how our silicon IP and tools are enabling adaptable, intelligent, industry leading systems. Xilinx will showcase the below demonstrations highlighting our Embedded, ML/AI, Alveo, Automotive and Industrial solutions.
Register for complimentary entrance to Embedded World using Xilinx code B401579.
|Embedded||Zynq UltraScale+ RFSoC Software Defined Radio||This Software Defined Radio demonstration showcases the Zynq® UltraScale+™ RFSoC multi-giga-sample RF data converters, and soft-decision forward error correction (SD-FEC), integrated into an SoC architecture. Complete with an Arm® Cortex™-A53 processing subsystem, UltraScale+ programmable logic, and the highest signal processing bandwidth in a Zynq UltraScale+ device, this family provides a comprehensive RF signal chain for wireless, cable access, test & measurement, early warning/radar, and other high performance RF applications.|
|Multi-stream Low Latency Video Codec Compliant with H.264 and H.265||Many applications for live video encoding require low latency like visual medical surgery equipment or Surveillance camera or Advanced Driver Assistance Systems (ADAS) which are highly dependent on video data real-time processing. The key metrics in live video application is the glass to glass latency. This low latency Video codec demonstration showcase supported multiple stream scenario with sub-frame latency mode which can be best suited for live video streaming kind of application.|
DesignStart FPGA – Cortex-M1
|Demonstration of hardware and software enablement on Xilinx devices of the Arm Cortex-M1 core, part of the Arm DesignStart FPGA program. MDK/Keil development tools directly interfacing to Cortex-M1 based subsystem instantiated on a FPGA based Arty-S7 Evaluation board. Real-time options can be updated to application design on the host laptop and downloaded to the board. ThreadX running for RTOS. Vivado® with Cortex-M1 design will be loaded and can be brought up for explanations of the Xilinx DesignStart FPGA flow.|
|ISM||Eight Channel Video Surveillance Analytics Appliances||Video analytics appliances are breathing new life into existing security systems by taking inputs from existing cameras and adding intelligence at the network. This demonstration shows how Xilinx enables simultaneous decode of eight H.264/H.265 video channels from different cameras and applies flexible and responsive AI in a single Zynq UltraScale+ MPSoC. Eight IP cameras (Xilinx or 3rd party) are sending compressed bitstream using a RTSP client to the appliance.|
|AWS IoT and Xilinx Mobilize Machine Learning Inference Applications from Cloud to Edge||This demonstrations shows how a Xilinx + AWS IoT enabled distributed control application can leverage the scale of AWS Cloud analytics, machine learning model building, application provisioning, and system dashboards. Based on an oil and gas industry scenario, we show how an industrial controller and intelligent I/O module can collaborate with AWS Cloud services through AWS Greengrass on Zynq Ultrascale+ and Amazon FreeRTOS on Xilinx Zynq-7000 platforms. The demonstration shows how one might enable an evolutionary application capability for long-lived systems through mobilizing a machine learning application from cloud to edge resulting in lower latency response and lower bandwidth requirements.|
|SPYN Featuring Python-based Predictive Maintenance||SPYN is Xilinx’s next generation easy-to-use motor control and analytics kit. Featuring the Zynq-7000 SoC, SPYN features a C language interface for the creation of accelerated motor control algorithms in FPGA fabric and the PYNQ framework for sensor data acquisition and processing with the help of popular Python libraries. Visualization and control of on-chip analytics and predictive maintenance algorithms occurs through a Jupyter Notebook interface driven by the on-chip Ubuntu webserver.|
|IDS NXT Vision App-based Camera Feauring Kortiq AIScale Machine Learning Accelerator||
The IDS NXT Platform is a series of Vision App-based industrial cameras for machine vision applications featuring Kortiq’s AIScale Machine Learning Accelerators embedded in Xilinx’s Zynq UltraScale+ MPSoC. The demo features a carousel of objects that are detected and recognized in tens of milliseconds by the low latency and low power Kortiq AIScale Accelerators implemented n FPGA logic. The Zynq UltraScale+ MPSoC is additionally mounted on Kortiq’s SOMIQ system-on-module for AI deployment made easy.
|Automotive||DRIVE-XA Automated Driving Development Platform||DRIVE-XA is Xilinx’s new automated driving development and path-finding platform. The platform offers customers a modular customizable heterogeneous processing environment with extensive sensor interfacing options. This demo will showcase the platform’s Data Aggregation, Pre-Processing, and Distribution (DAPD) functionality and feature Xylon’s 6-camera BSP framework which offers users an efficient starting point for their own IP development.|
|Deep Learning for ADAS Image Recognition||Multi-channel neural network processing for object detection with full automotive roadway scene segmentation and object detection and recognition. Demonstrates deep learning using CNN accelerators for a performance optimized ADAS solution. This demo uses the Zynq Ultrascale+ based ZCU102 platform running multi-neural network with four external cameras and loaded video stream.|
|Dynamic Function eXchange for ADAS using System View VSI Development Environment||DFX enables system developers to include mutually exclusive functions during system operation run-time in a single device. Due to device resource limitations, these functions would not be able to be utilized together. These resource limitations are addressed using partial reconfiguration where the functions are activated through DFX. Multiple functions such as forward camera view, rear camera view, biometrics and other mutually exclusive functions can now effectively be offered in a single device through a load on demand event trigger. Combined, these functions would require more resources than a single device would provide. Using System View VSI to partition and implement DFX, these functions can be offered for system operation during run-time. This demo showcases and ADAS solution for both rear and front camera to demonstrating DFX.|
|Alveo/Cloud||Analytics on the Edge on Alveo™ Accelerator Cards – Xelera Technologies GmbH||
The amount of data produced by devices at the edge is growing exponentially. Xelera analytics software provides a real-time capable solution for analyzing data on-the-fly in edge servers. Leveraging Xilinx Alveo™ accelerator cards, Xelera analytics library contains high-speed analytics and machine learning algorithms which can be used without code change at the application level.
|Adaptive Bitrate Transcoding on Alveo Accelerator Cards||Today video service providers manage bandwidth while guaranteeing effective video distribution by utilizing next-generation compression standards and Adaptive Bitrate (ABR) streaming protocols. Both of these approaches yield efficient results but increase computational complexity. Xilinx saw this challenge coming and began working with NGCodec and VYUsync to build a solution that would supply the necessary performance without requiring customers to significantly alter their existing infrastructure. Together, we are delivering an Alveo accelerated real-time H.264 to HEVC or VP9 ABR transcoder.|
Xilinx will be participating in the following conference sessions:
From DC to Daylight: Single Chip RF Solutions for Wired, Wireless and High Frequency
Wednesday, February 27 | 10:30 – 11:00
Conference Counter NCC Ost
Until recently FPGA devices were typically used for high speed data pre and post processing of RF signals, and were connected to external A/D and D/A converters. Recently direct-RF data converters have seen increased adoption, due to their unparalleled bandwidth and flexibility. There are now, in production, fully integrated FPGA devices with multi-giga-sample per second direct-RF A/D and D/A converters, Soft-Decision Forward Error Correction (SD-FEC) modules, and processing systems. These integrated devices enable single chip solutions for wired, wireless, narrowband, and long range IoT.
Direct RF sampling moves the A/D and D/A conversion process closer to the antenna such that the converter directly samples the RF signal. This technology allows analog/RF signal processing to be moved in to the digital domain enabling a more flexible and programmable solution to be delivered. Advantages include:
- Elimination of analog/RF signal processing and associated impairments
- Increased flexibility to support wider bandwidths and multiple operating RF bands
- Enablement of a software defined radio front end
- Reduced overall system cost, power and footprint
Delivering Real Time and Determinism of Zynq® UltraScale+™ A53 Clusters with Coloured Lockdown and Jailhouse Hypervisor
Wednesday, February 27 | 15:00 – 15:30
Conference Counter NCC Ost
Today’s market requirements are forcing increased computational requirement in all embedded applications using multicore and preservation of legacy real time code, often developed in decades for single core. Performances offered by real time processors are oftentimes not enough, leading designers to consider and use application processors to get the desired performance at expense of determinism and worst case execution time (WCET). This paper describes how to use the Arm Cortex® A53 Application Processor cluster for implementing real time asymmetric multiprocessing (RTAMP), improving worst case execution time (WCET), reducing latency, and isolating and partitioning the cluster such that software developed for single cores can be reused. Demand has flourished in Industrial, Automotive and Avionics applications because software architects want to use the cluster like a set of single cores for executing real time code. Shared resources like the level 2 cache and memory controller guarantee performances on average. Worst case execution time is affected by interference amongst cores when accessing shared caches and memories. Xilinx in collaboration with UniMore solved the challenge with Coloured Lockdown for shared cache management and improved predictability. Linux and baremetal isolated applications can run on designated cores using Jailhouse partitioning hypervisor. Hypervisor overhead is also reduced making the solution very compelling. The paper describes the excellent results obtained by this solution with benchmark and industrial use case.
Lowering Software Development Costs by Using Arm Cortex-M Processors in an FPGA
Thursday, February 28 | 14:00 – 14:30
Conference Counter NCC Ost
As design requirements and standards continue to evolve in the embedded market, FPGAs provide developers a great opportunity to get started on a project instantly, and incrementally improve the design over time. But how do you build a successful FPGA solution? Xilinx and Arm have joined forces to help embedded developers experience the benefits of a commercial FPGA, with the processing and software ecosystem of the Arm embedded processors. This white paper illustrates how to use Cortex-M processors in Xilinx-based FPGAs and the key steps you need to take in order to develop a successful FPGA-based device, including integration, verification, synthesis and software development.