Vitis Developer Series 2021

If you are a Software or AI developer looking to accelerate your applications, you don’t want to miss our free webinar series on Vitis™ and Vitis AI development environments! Learn about adapting the architecture of your deployment platforms to meet the growing challenges and unique requirements of your applications, while continuing to use high-level frameworks like TensorFlow and Caffe, and develop in familiar programming languages like C,C++ and Python.

Tune in every week where we will cover AI inferencing solutions, open-source performance-optimized libraries, comprehensive developer tools, and design methodology.  Click on your preferred time and register below for the modules you are most interested in!

Topic - Watch On-Demand
Abstract
Accelerating Deep Learning Models on Xilinx VCK5000 Xilinx 7nm Versal developer card for AI, VCK5000, is now available with one of the highest performance/$ scores on the latest MLPerf 1.0 benchmarks. Join this webinar to learn how to directly take your TensorFlow / Pytorch models and accelerate on the VCK5000 card. This session will cover the introduction of three overlays on CNN and NLP application with a demo showing how to get deep learning models running on VCK5000.
Exceed CPU and GPU Performance with Vitis C++ Kernels Designing C++ kernels is simpler than you might think... This session goes over the key optimizations for C++ kernels and shows how to take advantage of the inherent parallelism of an FPGA. The performance of a Xilinx device is compared to CPU and GPU through an NP algorithm, the compute-intensive "traveling salesman problem."
Embrace the Power of Adaptive Computing with Vitis Platforms Vitis platforms make acceleration applications portable from edge to cloud. Join this session to learn how Vitis platforms can help to boost your design speed and design your custom platform.
Advanced RTL Kernel Integration with Vitis ­­As an import hardware methodology, RTL design flow is strengthened rather than forgotten in Vitis. With a simple and straightforward flow, you can port your existing RTL design or start a new RTL design with Vitis easily and efficiently. This session will show some basic flows to finish the RTL kernel design and integration with Vitis Flow.

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