Booth Highlights

The following demos will be featured from Xilinx throughout the show.

Machine Learning Acceleration Stack on AWS Cloud
Machine learning demonstration on Amazon EC2 F1 instance showcasing over 10,000 images/sec. This illustrates how FPGA pooling produces a high performance, low power solution compared to an x86 solution. One single x86 can service eight FPGAs eliminating the need for a 1:1 ratio of x86 to FPGA.

Edge-to-Cloud Video Analytics
Demonstration of how Xilinx can accelerate both the development and deployment of real-time HD video applications with machine learning.  Showcases video processing and machine learning in a single system using industry standard frameworks FFmpeg and YOLO.  

FPGAs on AWS Cloud
Demonstration gives an overview of Amazon EC2 F1 instances and their capability to accelerate workloads such as data analytics, machine learning, video transcoding and genomics.

Storage and Network Acceleration
The Xilinx single-chip storage solution integrates NVMe-over-Fabric and targets RDMA offloads with a processing subsystem to provide a very power-efficient and low-latency solution compared to existing products that require both an external host chip and a Network Interface Card (NIC). This 2x100Gb Ethernet platform enables customers to implement value-added storage workload acceleration, such as compression and erasure code. In addition, Xilinx and Eideticom will demonstrate disaggregation of FPGA accelerators using Eideticom NoLoad™ and NVMe-over-Fabrics. 

CCIX Interconnect Standard
Demonstration showcasing the cache coherent interconnect for accelerators (CCIX) focused on emerging high performance acceleration applications. Illustrates packet forwarding acceleration for NFV platforms based on a CCIX capable CPU and Xilinx CCIX accelerator doing L2 forwarding and highlights how CCIX greatly simplifies data movement architecture between host and accelerators.

FPGA Accelerated AMD EPYC™ Server
Demonstration illustrating multi-accelerator machine learning inference using a Xilinx VU9P FPGA. This demo showcases the industry’s best 128 lanes of PCIe system bandwidth.

Booth Information

Xilinx Booth #681
Colorado Convention Center
Denver, CO

Monday, November 13
7:00 PM – 9:00 PM

Tuesday, November 14
10:00 AM – 6:00 PM

Wednesday, November 15
10:00 AM – 6:00 PM

Thursday, November 16
10:00 AM – 3:00 PM

Conference Participation

Xilinx Conference Participation
Xilinx experts will be participating in the following product showcases.

Reconfigurable Acceleration at Cloud Scale
Tuesday, November 14
11:00 AM
Location: AMD Booth #825

SC17 Exhibitor Forum: Khronos SYCL: Tomorrow’s Heterogeneous C++ and C Today
Tuesday, November 14
4:30 PM – 5:00 PM
Location: 503-504

SYCL is a Khronos specification for heterogeneous computing built on top of OpenCL and C++. The SYCL 1.2 specification was published on May 2015, and the current SYCL 2.2 specification has been published on February 2016. Behind these two specifications, there has been an important community effort ongoing for more than five years. Now the specifications are available and Codeplay is releasing their ComputeCpp Community Edition as well as optimized version commercially supported for many CPU+CPU/DSP/FPGA combinations.This talk will demonstrate how SYCL can be used today to support your exascale C++ effort, leading to ISO-ready C++ code that can support numerical computations on any compute node+gpu combinations, while staying with the current and future C++ standard direction for executors and heterogeneous computing.

BoF: Distributed and Heterogeneous Programming in C++ for HPC BoF
Wednesday, November 15
12:15 PM – 1:15 PM
Location: 405-406-407

In response to the HPC requirements from CORAL/SUMMIT to achieve exascale performance, we will discuss the programming models that support heterogeneous programming in C and C++ and future standardization work toward that exascale goal. We will discuss research in this domain and consolidate usage experience with the aim of passing that experience to ISO C and C++. There are a number of C++ frameworks for parallel programming, including HPX, KoKKos, Raja, C++AMP, HCC, Boost.Compute, CUDA, and more. SYCL from Khronos provides heterogeneous computing built on OpenCL and C++, and Codeplay has released ComputeCpp Community Edition.

Reconfigurable Supercomputing
Wednesday, November 15
5:15 PM – 6:45 PM
Location: 301-302-303

Reconfigurable Supercomputing (RSC) is characterized by hardware that adapts to match the needs of each application, offering unique advantages in performance per unit energy for high-end computing. 2017 continues breakout for RSC. Last year’s highlights included datacenter deployment by Microsoft, acquisition of Altera by Intel, and successful large-scale RSC in the NSF CHREC Center. This year is highlighted by deployment of publicly available RSC nodes and clusters by AWS and Baidu. This BoF introduces architectures of such systems, describes applications and tools being developed, and provides a forum for discussing emerging opportunities and issues for performance, productivity, and sustainability.

H2RC Workshop
Friday, November 17
8:30 AM – 12:00 PM
Location: 402-403

For the third year in a row, this workshop will bring together application experts, software developers, and hardware engineers to share experiences and best practices leveraging reconfigurable logic in HPC and “Big Data” applications. In particular, the workshop will focus on sharing experiences and techniques for accelerating applications and/or improving energy efficiency with FPGAs using OpenCL, OpenMP, OpenACC, C, and C++ based design flows, which enable and improve cross-platform functional and performance portability. Particular emphasis is given to cross-platform comparisons that foster a better understanding within the industry and research community on what are the best mappings of applications to a diverse range of hardware architectures that are available today (e.g., FPGA vs. GPU vs. Many-cores and hybrid devices), and on how to most effectively achieve cross-platform compatibility.

Click here for more information.

Xilinx Developer Lab

Xilinx Developer Lab: Accelerating Applications with FPGAs on AWS  

Wednesday, November 15, 2017
8AM-12PM (Mountain Time)

Denver Performing Arts Complex
The Studio Loft (across the Champa Street to the northwest)
1400 Curtis Street, Denver, CO 80204

Gain valuable hands-on experience in a developer lab hosted by Xilinx at SC17. Special guest speaker from Amazon Web Services.

Learn about AWS EC2 F1 instances and the data center workloads they accelerate, and hear F1 partners Ryft Systems and NGCodec discuss their experience with application acceleration using F1 instances. Learn from knowledgeable F1 developers and gain hands on experience using AWS EC2 F1 SDK to accelerate your applications.

Lab instruction time includes:

  1. Step-by-step instructions to connect to an F1 instance
  2. Interactive walkthrough of the SDAccel™ Development Environment
  3. Highlights of SDAccel IDE features: compile, debug, profile
  4. Instruction for how to develop a sample framework acceleration app

Xilinx, Amazon Web Services, Ryft, and NGCodec technology experts will be available onsite.

8:00AM                Doors open, registration, coffee, continental breakfast
8:30AM                Welcome, technology discussion, F1 developer use cases and demos 
9:35AM                Break
9:45AM                Hands on training begins
12PM                   Developer Lab concludes                       


Ecosystem Demonstrations

Xilinx Ecosystem Demonstrations
Xilinx technology-enabled demos can be found throughout the SC17show floor.

AlphaData – Booth 1838

AMD – Booth 825

BittWare – Booth 692

Dini – Booth 785

Gen-Z Consortium – Booth 992

Huawei – Booth 425

IntelliProp Inc. – Booth 250

Khronos Group – Booth 394

Mellanox – Booth 653

Metamako – Booth 670

Micron – Booth 1963

Nallatech/Molex – Booth 1362/1263

Netcope – Booth 970

NIMBIX – Booth 953

OpenCAPI Consortium – Booth    1587

Ryft – Booth 689

SmartIOPS – Booth 273