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Delivering a Generation Ahead at 20nm and 16nm

The Xilinx All Programmable product portfolio based on 28nm and 20nm planar and 16Fin FET+ technologies keeps customers a generation ahead of their competition with an expansion of its offerings from three perspectives:

  • Portfolio: UltraScale™ architecture-based All Programmable FPGAs, 3D ICs and SoCs
  • Product: Co-optimized with the Vivado™ Design Suite for extra performance, power, and integration
  • Productivity: Unmatched time to integration and implementation

UltraScale+ Family: Expanding the 20nm UltraScale Architecture

Xilinx is committed to staying a generation ahead with aggressive roadmaps across each of the three elements of its broader portfolio, with each element supporting and reinforcing the previous generation. With the addition of UltraScale+, Xilinx has built upon the UltraScale architecture which allows for simple migration between planar and FinFET nodes. This allows customers to migrate their 20nm designs and benefit from the performance per watt advantages of FinFET technology.

system-level

Figure 1: Xilinx continues to expand its leadership in all three areas.

Innovations at 16nm: UltraScale+ Family

Building on the core UltraScale architecture at 20nm, Xilinx’s 16nm UltraScale+™ family of FPGAs, 3D ICs and MPSoCs, combine new UltraRAM and High-Bandwidth Memory (HBM), 3D-on-3D and multi-processing SoC (MPSoC) technologies, delivering a generation ahead of value. To enable the highest level of performance and integration, the UltraScale+ family also includes a new interconnect optimization technology, SmartConnect. These devices extend Xilinx’s UltraScale portfolio - now spanning 20nm and 16nm FPGA, SoC and 3D IC devices - and leverage a significant boost in performance/watt from TSMC’s 16FF+ FinFET 3D transistors. Optimized at the system level, the UltraScale+ family delivers far more systems integration and intelligence, and the highest level of security and safety than previous generations of technology.

The newly extended Xilinx UltraScale+ FPGA portfolio is comprised of Xilinx’s market leading Kintex® UltraScale+ FPGA and Virtex® UltraScale+ FPGA and 3D IC families, while the Zynq® UltraScale+ family includes the industry’s first all programmable MPSoCs.

Zynq UltraScale+ MPSoC – The 2nd Generation All Programmable SoC

The UltraScale+™ MPSoC Architecture, built on TSMC’s 16nm FinFET process technology, enables next generation Zynq UltraScale MPSoCs. This new architecture provides processor scalability from 32 to 64 bits with support for virtualization, the combination of soft and hard engines for real time control, and graphics/video processing, waveform and packet processing, next generation interconnect and memory, advanced power management, and technology enhancements that deliver multi-level security, safety and reliability. These new architectural elements are coupled with the Vivado® Design Suite and abstract design environments to greatly simplify programming and increase productivity.

ultrascale_mpsoc_architecture

Figure2 : The Xilinx UltraScale MPSoC architecture delivers the right engines for the right tasks.

Industry’s First 3D on 3D Technology

The high end of the UltraScale+ portfolio leverages the combined power of 3D transistors and 3rd generation of Xilinx 3D ICs. Just as FinFETs enable a non-linear improvement in performance/watt over planar transistors, 3D ICs enable a non-linear improvement in systems integration and bandwidth/watt over monolithic devices.

2nd Generation All Programmable 3D IC

Figure 3: Xilinx’s 3rd generation 3D ICs will come in homogeneous and heterogeneous configurations.

Next Generation Design Suite & Methodology

Built from the ground up for Xilinx’s 28nm portfolio, the Vivado Design Suite has been co-optimized with the UltraScale architecture to deliver significant quality of results, routability, utilization, and productivity advantages. When combined with UltraFast™, a potent methodology that covers all aspects of board planning, design creation, design implementation and closure, programming and hardware debug, design teams will be able to accelerate their time to predictable success.

Productivity for the front end design process is multiplied by more than 4X with high level synthesis and IP integration tools. Productivity in design implementation improves by more than 4X due to faster hierarchical planning and analytic place and route engines as well as support for fast incremental ECOs.

Next Generation Design Suite

Figure 4: The Vivado Design Suite in conjunction with the UltraFast methodology enables unmatched time to integration and implementation.