UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Xilinx Security Working Group 2015

security-banner_europe

Stuttgart, Germany

November 17, 2015

09:00 - 18:00

Stuttgart Mariott Hotel Sindelfingen

>> Register Now

Paris, France

November 19, 2015

09:00 - 18:00

Mercure Paris Massy Gare TGV Hotel

>> Register Now

The Xilinx Security Working Group (XSWG) is a brand new one day event that brings together Xilinx aerospace, defense and commercial customers, academic representatives, Xilinx Alliance Members and government agencies to discuss the latest security topics including:

  • Supply Chain Protections
  • Device Security
  • Secure Boot
  • Runtime Security

Presentations from both Xilinx and external spokespeople will cover the following:

  • The latest information on security features and IP for today and tomorrow
  • How Xilinx’s latest FPGA and SoC devices meet the industry’s security requirements 
  • Security issues and requirements for Industrial, Automotive, A&D and Wired Communications markets that depend on FPGA and SoC technologies

The Xilinx Security Working Group provides an excellent forum for participation and collaboration among the attendees, and provides Xilinx a better understanding of the industry’s security requirements for today and tomorrow. 

Don’t miss this chance to discuss Xilinx’s latest technology innovations and solve your greatest design challenges.

2015 Xilinx Security Working Group (XSWG) EMEA Agenda

View complete agenda, click here.

Time Slot Topic Presenter
08:30 – 09:00 
Check-in
09:00 – 09:15 Welcome & Introductions

Jason Moore
Director: Mkt Segment Engineering, Xilinx

09:15 – 10:00 Next Generation Features / Survey  Jason Moore
Director: Mkt Segment Engineering, Xilinx
10:00 – 11:15 Zynq UltraScale+ MPSoC Security Capabilities Jason Moore
Director: Mkt Segment Engineering, Xilinx
11:15 – 11:30 Break
11:30 – 12:30 Run-Time Security for Zynq UltraScale+ MPSoC

Jim Wesselkamper
Director: Mkt Segment Engineering, Xilinx

12:30 – 13:30 Lunch 
13:30 – 14:00 Topic : Partner Presentation Pending TBD
14:00 – 14:45 Leveraging Asymmetric Authentication to Enhance Security in
Zynq-7000 and UltraScale FPGA Devices
Ed Peterson
Sr. Staff Application Engr, Xilinx
14:45 – 15:15 ISO/IEC 19790 Primer of the Zynq-7000 SoC Ed Peterson
Sr. Staff Application Engr, Xilinx
15:15 – 15:30 Break
15:30 – 16:30 Security Monitor and Stacked Silicon Interconnect Technology Jim Wesselkamper
Director: Mkt Segment Engineering, Xilinx
16:30 – 17:30 Isolation Design Flow Jason Moore
Director: Mkt Segment Engineering, Xilinx
17:30 – 18:00 Physical Sensor R&D Jim Wesselkamper
Director: Mkt Segment Engineering, Xilinx
18:00 Formal Adjournment
18:00 – 18:30 Next Gen Survey Results Discussion Jason Moore
Director: Mkt Segment Engineering, Xilinx

* Presenters, topics, and time slots subject to change – the final agenda will be supplied at the start of the XSWG.

Security 101 Video - Attendees – Please Watch In Advance!

Attendees – please watch this informative video prior to attending our Security Working Group event in either Stuttgart or Paris. This video will provide you with a basic understanding of the various definitions and disciplines associated with electronic device security.  The attack vectors specifically associated with FPGA and SoC devices are described (class of attack, complexity, etc.), in addition to device and run-time security.   Watch the video here

Quick Links

Page Bookmarked