CadEnhance provides tools to work with a customer's existing schematic EDA tools. They automate the error-prone tasks involved in creating schematics with Xilinx devices
PartBuilder creates schematic symbols for electronic devices. When building Xilinx FPGAs, PartBuilder extracts accurate pin-data for each pin including: physical and logical pinNames, pinNumber, pinType and pinDelay from the package and PinReport files.
In the XILINX_PHYSICAL flow, Smart-Frac and the Symbol Description Language enables users to create highly functional symbols pre-organized as groups of I/O Banks, for any Xilinx FPGA device from 100 to 4000+ pins in less than an hour.
In the XILINX_LOGICAL flow the logical pin_name is used so that symbol pin-names represent the functional name from the FPGA design. While symbol creation takes a little longer, the benefits of using the LOGICAL flow far outweigh the extra time required up-front.
FpgaPinPlanner manages Xilinx FPGA pinouts from initial creation through the final board design including full support for pin-swapping at the board Level. It can create an early pinout for a device from scratch, or migrate an existing pinout from one device to another It also use multiple constraint files to merge functions from pre-existing designs as a starting point for a new design.
CE-HDL (for AllegroHDL) The CE-HDL PinWire tool enables a user to magically wire the symbols in their schematic. PinWire provides a direct solution for the manual, error-prone task of making connections to a XILINX FPGA created using the PHYSICAL flow. It uses the compiled FPGA Pin-Report to create the logical connection names for each symbol pin selected in a bulk operation. PinWire works equally well with the LOGICAL flow since it can also make connection names based off the actual pin_name.
It can literally save engineers days to weeks per FPGA device on their board.