Leading performance icon

Leading Performance/Watt
for Cost-Sensitive Applications

gear and graph for high compute density

Highest Compute Density
with Ultra-Compact Form Factor

swilling arrows for scalability icon

Scalability Across
UltraScale+ FPGAs & SoCs

what's new

NEW ARTIX ULTRASCALE+ FPGA FAMILY

Four Cost-Optimized FPGAs from the Established 16nm UltraScale Architecture

New Artix UltraSCALE+ FPGA Family

Serial I/O
Performance

16Gb/s transceivers for advanced protocols in a cost-optimized family

Signal Processing
Compute Density

Best-in-class DSP bandwidth a small form factor package

Multi-Level
Security

Cryptography, authentication, and DPA resistance for cyber security and IP protection

Introducing the New ZU1 Device

Small—But Mighty

New ZU1 Device Diagram

Lowest Power, Lowest Cost Device in the Portfolio

Highest I/O-to-Logic Cell Ratio

Highest DSP-to-Logic Cell Ratio

Same Multiprocessing Arm® Processing System

HIGHEST COMPUTE DENSITY

InFO packaging enables highest compute density for AI and signal processing

Artix UltraScale+ chip

70%

Smaller

2.3X

DSP Bandwidth*

zynq ultrascale+ soc chip

60%

Smaller

5X

DMIPs/mm2**

InFO packaging available for the following devices

Device AU10P AU15P ZU1 CG/EG ZU2 CG/EG ZU3 CG/EG
Dimensions (mm) 9.5 x 11.5 9.5 x 11.5 9.5 x 15 9.5 x 16 9.5 x 16

* vs Artix-7 FPGAs
** vs competing ASSPs
Form Factor vs. Flip-Chip Packaging

SCALABLE ACROSS PROVEN 16nm Portfolio

The new Artix® UltraScale+™ FPGAs and Zynq® UltraScale+ MPSoCs are built on the proven 16nm UltraScale architecture, allowing developers to leverage the same software and tool flows, existing hardware IP, and the same safety and security certifications already established by UltraScale+ devices. Build your design once, and preserve your investment by scaling across your entire end portfolio.

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webinar

Artix UltraScale+ chip and zynq ultrascale+ zu1 chips

Want to learn more? Check out our OnDemand webinar highlighting the new Cost-Optimized FPGAs and SoCs.