FPGA-based prototyping is the process of implementing/synthesizing an ASIC RTL on a platform comprising one or more FPGAs. Prototyping is done before tape out as part of the pre-silicon system validation flow but can be used post tape out for software development. The prototyping platform also includes interfaces to peripherals and memories that are used with the targeted ASIC.
Hardware verification and SW/FW development are the dominant factors in SoC design cost. Before tape out, hardware and software co-validation during prototyping allows developers to bring up the software and implement custom features before physical parts are available. Moreover, the design flow can be co-optimized by using the AMD Vivado™ Design Suite, which reduces cost and tape out risk, and improves efficiency and time-to-market.
For FPGA-based prototyping, AMD solutions:
With the Virtex™ 7 2000T FPGA and the Virtex UltraScale™ VU440 FPGA, AMD has been the market leader for the highest capacity FPGAs. The 16nm Virtex UltraScale+™ family now includes the world’s largest FPGA, the Virtex UltraScale+ VU19P FPGA, achieving three consecutive generations of high-end leadership.
Built with SoC prototyping in mind
Extending device density lead to 4X at 20nm
Industry’s highest capacity FPGA
Breakthrough performance and integration for ASIC prototyping and emulation can be realized with AMD UltraScale™ architecture. Virtex™ UltraScale devices simplify design partitioning through high logic capacity, over 90% device utilization, ASIC-like clocking, enhanced routing, and high-speed transceivers for pin multiplexing. This breakthrough architecture coupled with Vivado™ Design Suite provides the ideal solution for tackling the demands of leading-edge ASIC and SoC platforms.