OS/RTOS & Hypervisors/Containers

AMD supports a wide offering of operating systems (OS) and real-time operating systems (RTOS), including support for the popular Yocto-based Linux. A common architecture among many IIoT edge embedded devices is a dual OS and RTOS approach to support IT/OT convergence. In this scenario, IT functions are performed within the boundaries of an OS, most commonly Linux on an application processor, with the OT functions performed within the boundaries of Linux with the PREEMPT_RT modifications, an RTOS, or FPGA hardware. In some cases, the RTOS runs on a real-time processor core and in other cases, it is desirable for both IT and OT functions to run on application processors due to performance, feature set, and ease of supporting one homogenous processor architecture.

However, control over application processing behaviors has attracted a lot of attention from Healthcare IoT developers due to the deterministic requirements of Healthcare tasks intersecting the inherently non-deterministic behavior of application processors, caches, and the applications themselves. Different approaches have been researched and adopted to maximize the both the capability and suitability of today’s modern single to multi-core embedded processors, many of which are supported by AMD SoCs.

One approach is through isolation: hypervisors isolate operating systems, containers isolate applications. Both create virtualized boxes that offer some degree of immunity from the behaviors of other boxes that may exist, which sometime contain independently-written 3^rd party content that has not been tested for interoperability or stability.

Other approaches involve making use of the low-level hardware architecture to monitor and control behavior, as is employed with unsupervised asymmetric processing (AMP) and cache coloring techniques. AMP uses multiple processors with precise control over what runs on each processor. Cache coloring is a hybrid approach that, often in conjunction with a hypervisor, enables exclusive access to the cache by a single processor core reducing the impact on timing of a cache eviction.