With the Wireless Trend of Densification, CRAN activity and Small Cell deployment for better coverage, the Fronthaul link is challenged both in Bandwidth (BW) and being able to service the heterogeneous networks being deployed. Xilinx offer solutions around switching needs to service the large number of remote radio heads (RRH) by the Baseband processing unit (IQ switching), a lightweight Ethernet switch for servicing a small number of RRH daisy chained or otherwise connected together, as well as IQ compression to effectively increase the Fronthaul bandwidth without using additional Fiber or other techniques.
This demo design utilizes the Xilinx CPRI IP, I/Q Switch IP, and Lightweight Ethernet Switch IP to provide an extendable and reconfigurable Fronthaul networking solution for interconnection between the centralized baseband processing resources and remote radio units. The demo implements a 16-port switch (8 slave serial BBU I/Fs and 8 master remote radio links) operating at CPRI rate 8 (10.137Gbps). Leveraging the Xilinx CPRI, I/Q switch, and Lightweight Ethernet Switch IP, this design provides a reference Fronthaul switching solution that is ideally suited for implementation on Xilinx UltraScale devices featuring ASIC-class serial transceivers.
A configurable CPRI switching solution is required to minimize the Fronthaul networking costs that are rising along with the bandwidth demands and the increasing physical distance between the baseband processing resources and remote radio units. Architectural developments like baseband processing centralization (CRAN) offer capital and operating cost benefits by the means of a better utilization of the shared network resources. However, the Fronthaul network flexibility is limited by the point-to-point BBU-RRU links.
A simplified wireless system shown in Figure 1 deploys a CPRI switch to increase the Fronthaul network flexibility. The illustrated example configuration shows how a centralized baseband processing pool can utilize a CPRI switch to connect to two remote sites hosting four antennas.
To learn more about Xilinx Wireless Communications Solutions, visit the Wireless IP and Reference Design page.
To enable switching on high-speed serial transceiver links a CPRI switch implements 8 CPRI IP cores on both its BBU and RRU interfaces. As illustrated in the Figure 2, the CPRI switching subsystem is configured and controlled via local microprocessor interfaces. The PoC design also includes the required clock generation and buffering resources.
Figure 3 illustrates the CPRI switching subsystem architecture showing the bus interface connections for a single path only to reduce the routing congestion. The serial links shown in red interface to the CPRI BBU and CPRI RRU subsystems that de-serialize the link data stream and enable the I/Q and Ethernet data switching on the corresponding IP interfaces. The downlink (blue) and uplink (green) I/Q data paths are routed via a synchronization block that manages the synchronization signals and aligns the uplink data stream. The Lightweight Ethernet switch provides a gigabit link (orange) to the BBU CPRI subsystem and 8 de-aggregated Ethernet links for each of the remote radio units. The CPRI and switching IP are configured via AXI4-Lite interfaces (grey) under microprocessor control.
Figure 2 - CPRI IQ Switch Design
Figure 3 –CPRI IQ Switch Architecture
The I/Q switch is capable of routing any ingress timeslot signal to any egress port timeslot. An ingress timeslot signal can also be routed to multiple egress ports (multicast / broadcast). To achieve this the switching fabric is implemented as a 2D array of BRAM which are configured as dual port memory. The ingress data frame is duplicated in each BRAM in a row so every egress port has access to any I/Q sample in a frame. An additional BRAM is used to provide a map so data from any timeslot in a frame can be routed to any timeslot on any egress port. Additional blocks provide de-skew and timing synchronization.
The switch architecture is based on sharing the available bandwidth between multiple downstream (radio) links where little Ethernet traffic is required during normal operation of the system. In the PoC example the 8 downstream CPRI links are connected via the aggregator/de-aggregator and share a single connection to the main switch. To simply the illustration, only 3 of the 8 CPRI radio links are shown in Figure 5
The CPRI switch components have been verified independently using the UVM methodology. The operation of the selected switch configuration has been verified in simulation.