With the Wireless Trend of Densification, CRAN activity and Small Cell deployment for better coverage, the Fronthaul link is challenged both in Bandwidth (BW) and being able to service the heterogeneous networks being deployed. Xilinx offer solutions around switching needs to service the large number of remote radio heads (RRH) by the Baseband processing unit (I/Q switching), a lightweight Ethernet switch for servicing a small number of RRH daisy chained or otherwise connected together, as well as I/Q compression to effectively increase the Fronthaul bandwidth without using additional Fiber or other techniques.
This Proof of Concept design provides an ETSI Open Radio equipment Interface (ORI) 4.1.1 CPRI™ I/Q compression /decompression (CODEC) module for 16 20 MHz antenna-carrier data streams to fully utilize a 9.8304 Gb/s CPRI link. The I/Q CODEC is implemented as a Vivado® High-Level Synthesis (HLS) IP enabling you to rapidly evaluate and optimize the CODEC performance for specific signal characteristics.
The I/Q CODEC reduces the Fronthaul infrastructure cost by lowering the escalating CPRI bandwidth requirements due to architectural changes. Such changes include baseband processing centralization (CRAN) and new network capabilities such as higher-order MIMO configurations and carrier aggregation.
A simplified application shown in Figure 1 illustrates the placement of compression and decompression modules at the CPRI I/Q input and output interface. Different bandwidth requirements and signal characteristics of the LTE downlink and uplink channels imply the use of channel-specific CODEC configurations. Alternatively, I/Q compression can be configured selectively for channels exceeding the available Fronthaul infrastructure bandwidth. Figure 1 also shows the alternative I/Q switch placement, before or after the I/Q compression module. The implications of I/Q switch design is discussed in detail in the Xilinx® White Paper, The Application of FPGAs for Wireless Base-Station Connectivity (WP450).
The Vivado HLS I/Q CODEC IP is designed to meet the throughput of three compressed E-UTRA samples (30-bits) per clock cycle. The 128-bit CPRI control word provides a sufficient buffer to fully pack the 32-bit CPRI I/Q interface. The re-sampling filter is implemented using four parallel polyphase fractional re-sampling filters, each filter compressing a subset (eight) of the supported 32 I and Q channels (see the Xilinx Application Note, Multi-Channel Fractional Sample Rate Conversion Filter Design Using Vivado High-Level Synthesis (XAPP1236) for more information). The proposed architecture reduces the CODEC latency because only a fraction of the coefficient set is used by each polyphase sub-filter. Figure 2 shows the I/Q CODEC architecture indicating sample processing rates at the compression IP interfaces.
Figure 2 – I/Q CODEC Architecture with Sample Processing Rates
The NLQ look-up table consists of 214 entries of 9-bit quantized values. The memory requirement for three parallel look-ups can be implemented using 18x18k block RAMs for the compression path. For decompression, assuming a symmetric I/Q distribution, the table size is limed to 29 entries of 14-bit values and is implemented in a single block RAM.
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The implemented CODEC algorithm was tested using a 20 MHz LTE E-UTRA FDD channel stimulus generated with MATLAB® LTE System Toolbox™. The Keysight VSA software was then used to demodulate the Vivado HLS simulation output and quantify the signal distortion due to the implemented CODEC stages by measuring the output waveform Error Vector Magnitude (EVM). Figure 3 shows the averaged EVM measurement of 0.29% for the tested CODEC configuration. Compared to the input data with EVM RMS of 0.18% the additional EVM attributable to the CODEC processing chain is therefore 0.23%.
Figure 3 - ORI I/Q CODEC input vs. output OFDMA constellation and signal spectrum VSA Measurements