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{"sheet":"Summary","index":0,"n_rows":12,"n_cols":3,"rows_kept":12,"cut":false,"hidden":false,"merged":[[0,1,0,2],[1,1,4,1],[1,2,5,2]]}
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[null,null,"Xilinx UltraScale Memory Interface Capacity Tool"]
[]
[]
[]
[null,"XMPxxx (v1.3) October 10, 2018"]
[]
[null,"PURPOSE","The \"# of Interaces\" tab shows a full summary of the maximum amount of each supported memory interface that can fit in the programmable logic (PL) of each Xilinx UltraScale, UltraScale+, and Zynq UltraScale+ MPSoC device.     \"Dynamic Assessment\" allows for a custom configuration and will show which  Xilinx UltraScale, UltraScale+, and Zynq UltraScale+ MPSoC  devices may be likeliest to support it in programmable logic (PL)."]
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[null,"DISCLAIMER","NOTICE OF DISCLAIMER: The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available \"AS IS\" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of Xilinx’s limited warranty, please refer to Xilinx’s Terms of Sale which can be viewed at at www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in such critical applications, please refer to Xilinx’s Terms of Sale which can be viewed at www.xilinx.com/legal.htm#tos."]
[]
[null,"COPYRIGHT","© Copyright 2012–2018 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. The PowerPC name and logo are registered trademarks of IBM Corp., and used under license. All other trademarks are the property of their respective owners."]

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[]
["INSTRUCTIONS:   \"# of Interfaces\"","The \"# of Interfaces\" tab will show you approximately how many of each memory interface can fit in each device's programmable logic (PL), assuming that memory interface is the only interface used in the device.   \nThis information can be helpful early in the planning stages where the designer knows the required number of a particular interface, and needs to know which devices can support that required quantity and which cannot.\nFor example, the KU040-SFVA784 can fit nine DDR3 x16 interfaces (of less than 512Mbits) if all available banks and byte lanes were used solely for this purpose.   \nThere are a few assumptions made when determining the quantities in this table:\n- All DDR3 & DDR4 interfaces utilize chip select, reset, and data mask\n- The system signals included are the system clock, system reset, init_calib_complete, and data_compare_error\n"]
[]
[]
["INSTRUCTIONS:   \"Dynamic Assessment\"","The \"Dynamic Assessment\" tab will allow you to experiment with various quantities of memory interfaces to determine which devices may be able to contain them all in programmable logic (PL).   This is useful if there are a variety of interfaces with various quantities in the design, and the designer is looking for a list of devices into which they might all fit.\nThe up and down arrows can be used to add or remove interfaces, or the desired amount can be directly typed into the \"QTY\" column.\nThere are two outcomes in the \"Dynamic Assessment\" columns:  \"Possibly\", and \"NO\".   \n- \"Possibly\" means that there is a chance all of the chosen interfaces (and quantities) can fit in the device.   Other circuitry or design constraints can mean the number of interfaces might not fit, so there can not be full certainty.\n- \"NO\" means that there is no chance the chosen interfaces (and quantities) can fit in the device.   \n"]

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["UltraScale/UltraScale+/Zynq UltraScale+ Memory Interface Maximum Capacities"]
["Depending on design needs, actual capacities may be lower.   Use only as a guide."]
["Scroll down for UltraScale+ and Zynq UltraScale+ MPSoC"]
[]
[null,null,"UltraScale",null,"Maximum amount of each interface that can fit on each device, assuming it's the only interface used"]
[null,null,"Die","Package","DDR3 x16 <=512M","DDR3 x16 >512M","DDR3 x32* <=512M","DDR3 x32* >512M","DDR3 x64 <=512M","DDR3 x64 >512M","DDR3 x72 <=512M","DDR3 x72 >512M","DDR4 x16 <=512M","DDR4 x16 >512M","DDR4 x32* <=512M","DDR4 x32* >512M","DDR4 x64 <=512M","DDR4 x64 >512M","DDR4 x72 <=512M","DDR4 x72 >512M","RLD3 X18","RLD3 X36","RLD3 x72","QDRII+ x36","QDRIV x36"]
[null,null,"KU025","FFVA1156",{"$f":"maxfit(C7,D7,\"DDR3X16_LE512M\")","v":6},{"$f":"maxfit(C7,D7,\"DDR3X16_G512M\")","v":3},{"$f":"maxfit(C7,D7,\"DDR3X32_LE512M\")","v":3},{"$f":"maxfit(C7,D7,\"DDR3X32_G512M\")","v":2},{"$f":"maxfit(C7,D7,\"DDR3X64_LE512M\")","v":1},{"$f":"maxfit(C7,D7,\"DDR3X64_G512M\")","v":1},{"$f":"maxfit(C7,D7,\"DDR3X72_LE512M\")","v":1},{"$f":"maxfit(C7,D7,\"DDR3X72_G512M\")","v":1},{"$f":"maxfit(C7,D7,\"DDR4X16_LE512M\")","v":4},{"$f":"maxfit(C7,D7,\"DDR4X16_G512M\")","v":2},{"$f":"maxfit(C7,D7,\"DDR4X32_LE512M\")","v":2},{"$f":"maxfit(C7,D7,\"DDR4X32_G512M\")","v":1},{"$f":"maxfit(C7,D7,\"DDR4X64_LE512M\")","v":1},{"$f":"maxfit(C7,D7,\"DDR4X64_G512M\")","v":1},{"$f":"maxfit(C7,D7,\"DDR4X72_LE512M\")","v":1},{"$f":"maxfit(C7,D7,\"DDR4X72_G512M\")","v":1},{"$f":"maxfit(C7,D7,\"RLD3X18\")","v":2},{"$f":"maxfit(C7,D7,\"RLD3X36\")","v":1},{"$f":"maxfit(C7,D7,\"RLD3X72\")","v":1},{"$f":"maxfit(C7,D7,\"QDRIIPX36\")","v":1},{"$f":"maxfit(C7,D7,\"QDRIVX36\")","v":1}]
[null,null,"KU035","SFVA784",{"$f":"maxfit(C8,D8,\"DDR3X16_LE512M\")","v":9},{"$f":"maxfit(C8,D8,\"DDR3X16_G512M\")","v":6},{"$f":"maxfit(C8,D8,\"DDR3X32_LE512M\")","v":5},{"$f":"maxfit(C8,D8,\"DDR3X32_G512M\")","v":4},{"$f":"maxfit(C8,D8,\"DDR3X64_LE512M\")","v":2},{"$f":"maxfit(C8,D8,\"DDR3X64_G512M\")","v":2},{"$f":"maxfit(C8,D8,\"DDR3X72_LE512M\")","v":2},{"$f":"maxfit(C8,D8,\"DDR3X72_G512M\")","v":2},{"$f":"maxfit(C8,D8,\"DDR4X16_LE512M\")","v":7},{"$f":"maxfit(C8,D8,\"DDR4X16_G512M\")","v":5},{"$f":"maxfit(C8,D8,\"DDR4X32_LE512M\")","v":4},{"$f":"maxfit(C8,D8,\"DDR4X32_G512M\")","v":3},{"$f":"maxfit(C8,D8,\"DDR4X64_LE512M\")","v":2},{"$f":"maxfit(C8,D8,\"DDR4X64_G512M\")","v":2},{"$f":"maxfit(C8,D8,\"DDR4X72_LE512M\")","v":2},{"$f":"maxfit(C8,D8,\"DDR4X72_G512M\")","v":2},{"$f":"maxfit(C8,D8,\"RLD3X18\")","v":4},{"$f":"maxfit(C8,D8,\"RLD3X36\")","v":3},{"$f":"maxfit(C8,D8,\"RLD3X72\")","v":2},{"$f":"maxfit(C8,D8,\"QDRIIPX36\")","v":2},{"$f":"maxfit(C8,D8,\"QDRIVX36\")","v":2}]
[null,null,"KU035","FBVA676",{"$f":"maxfit(C9,D9,\"DDR3X16_LE512M\")","v":6},{"$f":"maxfit(C9,D9,\"DDR3X16_G512M\")","v":3},{"$f":"maxfit(C9,D9,\"DDR3X32_LE512M\")","v":3},{"$f":"maxfit(C9,D9,\"DDR3X32_G512M\")","v":2},{"$f":"maxfit(C9,D9,\"DDR3X64_LE512M\")","v":1},{"$f":"maxfit(C9,D9,\"DDR3X64_G512M\")","v":1},{"$f":"maxfit(C9,D9,\"DDR3X72_LE512M\")","v":1},{"$f":"maxfit(C9,D9,\"DDR3X72_G512M\")","v":1},{"$f":"maxfit(C9,D9,\"DDR4X16_LE512M\")","v":4},{"$f":"maxfit(C9,D9,\"DDR4X16_G512M\")","v":2},{"$f":"maxfit(C9,D9,\"DDR4X32_LE512M\")","v":2},{"$f":"maxfit(C9,D9,\"DDR4X32_G512M\")","v":1},{"$f":"maxfit(C9,D9,\"DDR4X64_LE512M\")","v":1},{"$f":"maxfit(C9,D9,\"DDR4X64_G512M\")","v":1},{"$f":"maxfit(C9,D9,\"DDR4X72_LE512M\")","v":1},{"$f":"maxfit(C9,D9,\"DDR4X72_G512M\")","v":1},{"$f":"maxfit(C9,D9,\"RLD3X18\")","v":2},{"$f":"maxfit(C9,D9,\"RLD3X36\")","v":1},{"$f":"maxfit(C9,D9,\"RLD3X72\")","v":1},{"$f":"maxfit(C9,D9,\"QDRIIPX36\")","v":1},{"$f":"maxfit(C9,D9,\"QDRIVX36\")","v":1}]
[null,null,"KU035","FFVA900",{"$f":"maxfit(C10,D10,\"DDR3X16_LE512M\")","v":9},{"$f":"maxfit(C10,D10,\"DDR3X16_G512M\")","v":6},{"$f":"maxfit(C10,D10,\"DDR3X32_LE512M\")","v":5},{"$f":"maxfit(C10,D10,\"DDR3X32_G512M\")","v":4},{"$f":"maxfit(C10,D10,\"DDR3X64_LE512M\")","v":2},{"$f":"maxfit(C10,D10,\"DDR3X64_G512M\")","v":1},{"$f":"maxfit(C10,D10,\"DDR3X72_LE512M\")","v":1},{"$f":"maxfit(C10,D10,\"DDR3X72_G512M\")","v":1},{"$f":"maxfit(C10,D10,\"DDR4X16_LE512M\")","v":7},{"$f":"maxfit(C10,D10,\"DDR4X16_G512M\")","v":5},{"$f":"maxfit(C10,D10,\"DDR4X32_LE512M\")","v":4},{"$f":"maxfit(C10,D10,\"DDR4X32_G512M\")","v":3},{"$f":"maxfit(C10,D10,\"DDR4X64_LE512M\")","v":2},{"$f":"maxfit(C10,D10,\"DDR4X64_G512M\")","v":1},{"$f":"maxfit(C10,D10,\"DDR4X72_LE512M\")","v":1},{"$f":"maxfit(C10,D10,\"DDR4X72_G512M\")","v":1},{"$f":"maxfit(C10,D10,\"RLD3X18\")","v":4},{"$f":"maxfit(C10,D10,\"RLD3X36\")","v":3},{"$f":"maxfit(C10,D10,\"RLD3X72\")","v":1},{"$f":"maxfit(C10,D10,\"QDRIIPX36\")","v":1},1]
[null,null,"KU035","FFVA1156",10,7,6,4,3,2,2,2,{"$f":"maxfit(C11,D11,\"DDR4X16_LE512M\")","v":8},6,5,3,3,2,2,2,5,3,2,2,{"$f":"maxfit(C11,D11,\"QDRIVX36\")","v":2}]
[null,null,"KU040","SFVA784",9,6,5,4,2,2,2,2,{"$f":"maxfit(C12,D12,\"DDR4X16_LE512M\")","v":7},5,4,3,2,2,2,2,4,3,2,2,2]
[null,null,"KU040","FBVA676",{"$f":"maxfit(C13,D13,\"DDR3X16_LE512M\")","v":6},{"$f":"maxfit(C13,D13,\"DDR3X16_G512M\")","v":3},{"$f":"maxfit(C13,D13,\"DDR3X32_LE512M\")","v":3},{"$f":"maxfit(C13,D13,\"DDR3X32_G512M\")","v":2},{"$f":"maxfit(C13,D13,\"DDR3X64_LE512M\")","v":1},{"$f":"maxfit(C13,D13,\"DDR3X64_G512M\")","v":1},{"$f":"maxfit(C13,D13,\"DDR3X72_LE512M\")","v":1},{"$f":"maxfit(C13,D13,\"DDR3X72_G512M\")","v":1},{"$f":"maxfit(C13,D13,\"DDR4X16_LE512M\")","v":4},{"$f":"maxfit(C13,D13,\"DDR4X16_G512M\")","v":2},{"$f":"maxfit(C13,D13,\"DDR4X32_LE512M\")","v":2},{"$f":"maxfit(C13,D13,\"DDR4X32_G512M\")","v":1},{"$f":"maxfit(C13,D13,\"DDR4X64_LE512M\")","v":1},{"$f":"maxfit(C13,D13,\"DDR4X64_G512M\")","v":1},{"$f":"maxfit(C13,D13,\"DDR4X72_LE512M\")","v":1},{"$f":"maxfit(C13,D13,\"DDR4X72_G512M\")","v":1},{"$f":"maxfit(C13,D13,\"RLD3X18\")","v":2},{"$f":"maxfit(C13,D13,\"RLD3X36\")","v":1},{"$f":"maxfit(C13,D13,\"RLD3X72\")","v":1},{"$f":"maxfit(C13,D13,\"QDRIIPX36\")","v":1},{"$f":"maxfit(C13,D13,\"QDRIVX36\")","v":1}]
[null,null,"KU040","FFVA900",9,6,5,4,2,1,1,1,7,5,4,3,2,1,1,1,4,3,1,1,1]
[null,null,"KU040","FFVA1156",10,7,6,4,3,2,2,2,{"$f":"maxfit(C15,D15,\"DDR4X16_LE512M\")","v":8},6,5,3,3,2,2,2,5,3,2,2,2]
[null,null,"KU060","FFVA1156",10,7,6,4,3,2,2,2,8,6,5,3,3,2,2,2,5,3,2,2,2]
[null,null,"KU060","FFVA1517",12,8,7,5,3,2,2,2,10,7,6,4,3,2,2,2,6,4,2,2,2]
[null,null,"KU085","FLVA1517",12,8,7,5,3,2,2,2,10,7,6,4,3,2,2,2,6,4,2,2,2]
[null,null,"KU085","FLVB1760",12,8,6,5,3,2,2,2,11,8,6,5,3,2,2,2,6,5,2,2,2]
[null,null,"KU085","FLVF1924",12,6,6,4,2,2,2,2,10,6,6,4,2,2,2,2,6,4,2,2,2]
[null,null,"KU095","FFVA1156",{"$f":"maxfit(C21,D21,\"DDR3X16_LE512M\")","v":10},{"$f":"maxfit(C21,D21,\"DDR3X16_G512M\")","v":7},{"$f":"maxfit(C21,D21,\"DDR3X32_LE512M\")","v":5},{"$f":"maxfit(C21,D21,\"DDR3X32_G512M\")","v":4},{"$f":"maxfit(C21,D21,\"DDR3X64_LE512M\")","v":3},{"$f":"maxfit(C21,D21,\"DDR3X64_G512M\")","v":2},{"$f":"maxfit(C21,D21,\"DDR3X72_LE512M\")","v":2},{"$f":"maxfit(C21,D21,\"DDR3X72_G512M\")","v":2},{"$f":"maxfit(C21,D21,\"DDR4X16_LE512M\")","v":9},{"$f":"maxfit(C21,D21,\"DDR4X16_G512M\")","v":7},{"$f":"maxfit(C21,D21,\"DDR4X32_LE512M\")","v":5},{"$f":"maxfit(C21,D21,\"DDR4X32_G512M\")","v":4},{"$f":"maxfit(C21,D21,\"DDR4X64_LE512M\")","v":3},{"$f":"maxfit(C21,D21,\"DDR4X64_G512M\")","v":2},{"$f":"maxfit(C21,D21,\"DDR4X72_LE512M\")","v":2},{"$f":"maxfit(C21,D21,\"DDR4X72_G512M\")","v":2},{"$f":"maxfit(C21,D21,\"RLD3X18\")","v":5},{"$f":"maxfit(C21,D21,\"RLD3X36\")","v":4},{"$f":"maxfit(C21,D21,\"RLD3X72\")","v":2},{"$f":"maxfit(C21,D21,\"QDRIIPX36\")","v":2},{"$f":"maxfit(C21,D21,\"QDRIVX36\")","v":2}]
[null,null,"KU095","FFVC1517",9,7,5,4,3,2,2,2,9,7,5,4,3,2,2,2,5,4,2,2,2]
[null,null,"KU095","FFVB1760",12,8,7,6,3,3,3,3,12,8,7,6,3,3,3,3,7,5,{"$f":"maxfit(C23,D23,\"RLD3X72\")","v":3},3,3]
[null,null,"KU095","FFVB2104",12,8,8,4,4,4,4,4,12,8,8,4,4,4,4,4,8,4,4,4,4]
[null,null,"KU115","FLVA1517",12,8,7,5,3,2,2,2,10,7,6,4,3,2,2,2,6,4,2,2,2]
[null,null,"KU115","FLVD1517",6,3,3,2,1,1,1,1,5,3,3,2,1,1,1,1,3,2,1,1,1]
[null,null,"KU115","FLVB1760",12,8,6,5,3,2,2,2,11,8,6,5,3,2,2,2,6,5,2,2,2]
[null,null,"KU115","FLVD1924",15,9,7,6,3,3,3,3,13,9,7,6,3,3,3,3,7,6,3,3,3]
[null,null,"KU115","FLVF1924",14,8,8,4,4,4,4,4,12,8,8,4,4,4,4,4,8,4,4,4,4]
[null,null,"KU115","FLVA2104",15,9,7,6,3,3,3,3,13,9,7,6,3,3,3,3,7,6,3,3,3]
[null,null,"KU115","FLVB2104",12,7,7,4,3,3,3,3,11,7,7,4,3,3,3,3,7,4,3,3,3]
[null,null,"VU065","FFVC1517",9,7,5,4,3,2,2,2,9,7,5,4,3,2,2,2,5,4,2,2,2]
[null,null,"VU080","FFVC1517",9,7,5,4,3,2,2,2,9,7,5,4,3,2,2,2,5,4,2,2,2]
[null,null,"VU080","FFVD1517",6,4,4,2,2,2,2,2,6,4,4,2,2,2,2,2,4,2,2,2,2]
[null,null,"VU080","FFVB1760",12,8,7,6,3,3,3,3,12,8,7,6,3,3,3,3,7,5,3,3,3]
[null,null,"VU080","FFVA2104",15,11,9,8,5,4,4,4,15,11,9,8,5,4,4,4,9,7,4,4,4]
[null,null,"VU080","FFVB2104",12,8,8,4,4,4,4,4,12,8,8,4,4,4,4,4,8,4,4,4,4]
[null,null,"VU095","FFVC1517",9,7,5,4,3,2,2,2,9,7,5,4,3,2,2,2,5,4,2,2,2]
[null,null,"VU095","FFVD1517",6,4,4,2,2,2,2,2,6,4,4,2,2,2,2,2,4,2,2,2,2]
[null,null,"VU095","FFVB1760",12,8,7,6,3,3,3,3,12,8,7,6,3,3,3,3,7,5,3,3,3]
[null,null,"VU095","FFVA2104",15,11,9,8,5,4,4,4,15,11,9,8,5,4,4,4,9,7,4,4,4]
[null,null,"VU095","FFVB2104",12,8,8,4,4,4,4,4,12,8,8,4,4,4,4,4,8,4,4,4,4]
[null,null,"VU095","FFVC2104",7,5,4,4,2,2,2,2,7,5,4,4,2,2,2,2,4,3,2,2,2]
[null,null,"VU125","FLVD1517",6,4,4,2,2,2,2,2,6,4,4,2,2,2,2,2,4,2,2,2,2]
[null,null,"VU125","FLVB1760",12,9,7,5,4,3,3,3,12,9,7,5,4,3,3,3,7,5,3,3,3]
[null,null,"VU125","FLVA2104",15,11,8,7,4,4,4,4,15,11,8,7,4,4,4,4,8,7,4,4,4]
[null,null,"VU125","FLVB2104",12,8,8,4,4,4,4,4,12,8,8,4,4,4,4,4,8,4,4,4,4]
[null,null,"VU125","FLVC2104",7,5,4,3,2,2,2,2,7,5,4,3,2,2,2,2,4,3,2,2,2]
[null,null,"VU160","FLGB2104",12,8,8,4,4,4,4,4,12,8,8,4,4,4,4,4,8,4,4,4,4]
[null,null,"VU160","FLGC2104",7,5,4,3,2,2,2,2,7,5,4,3,2,2,2,2,4,3,2,2,2]
[null,null,"VU190","FLGB2104",12,8,8,4,4,4,4,4,12,8,8,4,4,4,4,4,8,4,4,4,4]
[null,null,"VU190","FLGC2104",7,5,4,3,2,2,2,2,7,5,4,3,2,2,2,2,4,3,2,2,2]
[null,null,"VU190","FLGA2577",8,4,4,2,2,2,2,2,8,4,4,2,2,2,2,2,4,2,2,2,2]
[null,null,"VU440","FLGB2377",24,18,12,12,6,6,6,6,24,18,12,12,6,6,6,6,12,12,6,6,6]
[null,null,"VU440","FLGA2892",27,21,15,12,9,6,6,6,27,21,15,12,9,6,6,6,15,12,6,6,6]
[]
[]
[null,null,"UltraScale+ ",null,"Maximum amount of each interface that can fit on each device, assuming it's the only interface used"]
[null,null,"Die","Package","DDR3 x16 <=512M","DDR3 x16 >512M","DDR3 x32* <=512M","DDR3 x32* >512M","DDR3 x64 <=512M","DDR3 x64 >512M","DDR3 x72 <=512M","DDR3 x72 >512M","DDR4 x16 <=512M","DDR4 x16 >512M","DDR4 x32* <=512M","DDR4 x32* >512M","DDR4 x64 <=512M","DDR4 x64 >512M","DDR4 x72 <=512M","DDR4 x72 >512M","RLD3 X18","RLD3 X36","RLD3 x72","QDRII+ x36","QDRIV x36"]
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[null,null,"VU5P","FLVA2104",16,12,8,8,4,4,4,4,16,12,8,8,4,4,4,4,8,8,4,4,4]
[null,null,"VU5P","FLVB2104",13,9,8,5,4,4,4,4,13,9,8,5,4,4,4,4,8,5,4,4,4]
[null,null,"VU5P","FLVC2104",8,6,5,3,3,2,2,2,8,6,5,3,3,2,2,2,5,3,2,2,2]
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[null,null,"VU7P","FLVB2104",13,9,8,5,4,4,4,4,13,9,8,5,4,4,4,4,8,5,4,4,4]
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[null,null,"VU9P","FLGA2577",8,4,4,2,2,2,2,2,8,4,4,2,2,2,2,2,4,2,2,2,2]
[null,null,"VU11P","FLGF1924",12,9,6,6,3,3,3,3,12,9,6,6,3,3,3,3,6,6,3,3,3]
[null,null,"VU11P","FLGB2104",11,8,6,5,3,3,3,3,11,8,6,5,3,3,3,3,6,5,3,3,3]
[null,null,"VU11P","FLGC2104",8,6,4,4,2,2,2,2,8,6,4,4,2,2,2,2,4,4,2,2,2]
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[null,null,"VU11P","FLGA2577",8,5,4,3,2,2,2,2,8,5,4,3,2,2,2,2,4,3,2,2,2]
[null,null,"VU13P","FHGA2104",16,12,8,8,4,4,4,4,16,12,8,8,4,4,4,4,8,8,4,4,4]
[null,null,"VU13P","FHGB2104",13,9,8,5,4,4,4,4,13,9,8,5,4,4,4,4,8,5,4,4,4]
[null,null,"VU13P","FHGC2104",8,6,4,4,2,2,2,2,8,6,4,4,2,2,2,2,4,4,2,2,2]
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[null,null,"VU29P","FSGA2577",8,4,4,2,2,2,2,2,8,4,4,2,2,2,2,2,4,2,2,2,2]
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[null,null,"VU33P","FSVH2104",4,3,2,2,1,1,1,1,4,3,2,2,1,1,1,1,2,2,1,1,1]
[null,null,"VU35P","FSVH2104",8,6,4,4,2,2,2,2,8,6,4,4,2,2,2,2,4,4,2,2,2]
[null,null,"VU35P","FSVH2892",8,6,4,4,2,2,2,2,8,6,4,4,2,2,2,2,4,4,2,2,2]
[null,null,"VU37P","FSVH2892",12,9,6,6,3,3,3,3,12,9,6,6,3,3,3,3,6,6,3,3,3]
[]
[]
[null,null,"Zynq UltraScale+  MPSoC",null,"Maximum amount of each interface that can fit on each device in Programmable Logic (PL), assuming it's the only interface used"]
[null,null,"Die","Package","DDR3 x16 <=512M","DDR3 x16 >512M","DDR3 x32* <=512M","DDR3 x32* >512M","DDR3 x64 <=512M","DDR3 x64 >512M","DDR3 x72 <=512M","DDR3 x72 >512M","DDR4 x16 <=512M","DDR4 x16 >512M","DDR4 x32* <=512M","DDR4 x32* >512M","DDR4 x64 <=512M","DDR4 x64 >512M","DDR4 x72 <=512M","DDR4 x72 >512M","RLD3 X18","RLD3 X36","RLD3 x72","QDRII+ x36","QDRIV x36"]
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[null,null,"ZU2CG","SFVA625",3,2,2,1,1,1,1,1,3,2,2,1,1,1,1,1,2,1,1,1,1]
[null,null,"ZU2CG","SFVC784",3,2,2,1,1,1,1,1,3,2,2,1,1,1,1,1,2,1,1,1,1]
[null,null,"ZU3CG","SBVA484",1,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0]
[null,null,"ZU3CG","SFVA625",3,2,2,1,1,1,1,1,3,2,2,1,1,1,1,1,2,1,1,1,1]
[null,null,"ZU3CG","SFVC784",3,2,2,1,1,1,1,1,3,2,2,1,1,1,1,1,2,1,1,1,1]
[null,null,"ZU4CG","SFVC784",3,2,2,1,1,1,1,1,3,2,2,1,1,1,1,1,2,1,1,1,1]
[null,null,"ZU4CG","FBVB900",3,2,2,1,1,1,1,1,3,2,2,1,1,1,1,1,2,1,1,1,1]
[null,null,"ZU5CG","SFVC784",3,2,2,1,1,1,1,1,3,2,2,1,1,1,1,1,2,1,1,1,1]
[null,null,"ZU5CG","FBVB900",3,2,2,1,1,1,1,1,3,2,2,1,1,1,1,1,2,1,1,1,1]
[null,null,"ZU6CG","FFVC900",3,2,2,1,1,1,1,1,3,2,2,1,1,1,1,1,2,1,1,1,1]
[null,null,"ZU6CG","FFVB1156",4,3,2,2,1,1,1,1,4,3,2,2,1,1,1,1,2,2,1,1,1]
[null,null,"ZU7CG","FBVB900",3,2,2,1,1,1,1,1,3,2,2,1,1,1,1,1,2,1,1,1,1]
[null,null,"ZU7CG","FFVC1156",6,4,3,2,2,1,1,1,6,4,3,2,2,1,1,1,3,2,1,1,1]
[null,null,"ZU7CG","FFVF1517",8,5,5,4,2,2,2,2,8,5,5,4,2,2,2,2,5,4,2,2,2]
[null,null,"ZU9CG","FFVC900",3,2,2,1,1,1,1,1,3,2,2,1,1,1,1,1,2,1,1,1,1]
[null,null,"ZU9CG","FFVB1156",4,3,2,2,1,1,1,1,4,3,2,2,1,1,1,1,2,2,1,1,1]
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{"sheet":"Dynamic Assessment","index":3,"n_rows":35,"n_cols":37,"rows_kept":35,"cut":false,"hidden":false,"merged":[[3,26,3,27],[3,30,3,31],[3,34,3,35],[3,22,3,23],[3,6,3,7],[3,10,3,11],[3,14,3,15],[3,18,3,19]]}
["Dynamic Assessment"]
["Check various combinations and quantities of"]
[" interfaces against all FPGA density/package pairs"]
[null,null,"QTY",null,null,null,"Kintex UltraScale",null,"Will It Fit?",null,"Virtex UltraScale",null,"Will It Fit?",null,"Kintex UltraScale+",null,"Will It Fit?",null,"Virtex UltraScale+",null,"Will It Fit?",null,"Zynq UltraScale+ CG",null,"Will It Fit?",null,"Zynq UltraScale+ EG",null,"Will It Fit?",null,"Zynq UltraScale+ EV",null,"Will It Fit?",null,"ZU+ RFSoC",null,"Will It Fit?"]
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{"sheet":"Revision History","index":4,"n_rows":9,"n_cols":4,"rows_kept":9,"cut":false,"hidden":false,"merged":[[1,1,1,3]]}
[]
[null,"Revision History"]
[null,"Date","Version","Revision"]
[null,"2016-03-18",1,"Initial Release"]
[null,"2016-09-13",1.1000000000000001,"Added D2104 Devices"]
[null,"2018-04-17",1.2,"Added HBM Devices"]
[null,null,null,"Added RFSoC Devices"]
[null,null,null,"Separated out CG, EG, and EV Devices"]
[null,"2018-10-10",1.3,"Added VU27P and VU29P Devices"]