Resource Utilization for Aurora 8B10B v11.1

Vivado Design Suite Release 2023.2

Interpreting the results

This page contains resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Kintex-7

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
C_AURORA_LANES
Dataflow_Config
Interface_Mode
C_GT_LOC_16
C_GT_LOC_15
C_GT_LOC_14
C_GT_LOC_13
C_GT_LOC_12
C_GT_LOC_11
C_GT_LOC_10
C_GT_LOC_9
C_GT_LOC_8
C_GT_LOC_7
C_GT_LOC_6
C_GT_LOC_5
C_GT_LOC_4
C_GT_LOC_3
C_GT_LOC_2
C_GT_LOC_1
C_GT_CLOCK_1
C_GT_CLOCK_2
SINGLEEND_INITCLK
SINGLEEND_GTREFCLK
SupportLevel
Fixed clocks (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7k325t ffg900 2 aurora_8b10b_dup_x16_frm 16 Duplex Framing 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 GTXQ1 GTXQ3 true true 1 DUT/inst/my_ip_core_i/gt_wrapper_i/my_ip_multi_gt_i/gt8_my_ip_i/gtxe2_i/TXOUTCLK=156 drpclk_in=50 gt_refclk1=125 gt_refclk2=125 init_clk_in=50 5354 7276 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 2 aurora_8b10b_dup_x16_strm 16 Duplex Streaming 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 GTXQ1 GTXQ3 true true 1 DUT/inst/my_ip_core_i/gt_wrapper_i/my_ip_multi_gt_i/gt8_my_ip_i/gtxe2_i/TXOUTCLK=156 drpclk_in=50 gt_refclk1=125 gt_refclk2=125 init_clk_in=50 2309 4506 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 2 aurora_8b10b_dup_x1_frm 1 Duplex Framing X X X X X X X X X X X X X X X 1 GTXQ0 None true true 1 DUT/inst/my_ip_core_i/gt_wrapper_i/my_ip_multi_gt_i/gt0_my_ip_i/gtxe2_i/TXOUTCLK=156 drpclk_in=50 gt_refclk1=125 init_clk_in=50 447 827 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 2 aurora_8b10b_dup_x1_strm 1 Duplex Streaming X X X X X X X X X X X X X X X 1 GTXQ0 None true true 1 DUT/inst/my_ip_core_i/gt_wrapper_i/my_ip_multi_gt_i/gt0_my_ip_i/gtxe2_i/TXOUTCLK=156 drpclk_in=50 gt_refclk1=125 init_clk_in=50 424 717 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 2 aurora_8b10b_dup_x2_frm 2 Duplex Framing X X X X X X X X X X X X X X 2 1 GTXQ0 None true true 1 DUT/inst/my_ip_core_i/gt_wrapper_i/my_ip_multi_gt_i/gt0_my_ip_i/gtxe2_i/TXOUTCLK=156 drpclk_in=50 gt_refclk1=125 init_clk_in=50 669 1210 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 2 aurora_8b10b_dup_x2_strm 2 Duplex Streaming X X X X X X X X X X X X X X 2 1 GTXQ0 None true true 1 DUT/inst/my_ip_core_i/gt_wrapper_i/my_ip_multi_gt_i/gt0_my_ip_i/gtxe2_i/TXOUTCLK=156 drpclk_in=50 gt_refclk1=125 init_clk_in=50 567 992 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 2 aurora_8b10b_dup_x4_frm 4 Duplex Framing X X X X X X X X X X X X 4 3 2 1 GTXQ0 None true true 1 DUT/inst/my_ip_core_i/gt_wrapper_i/my_ip_multi_gt_i/gt2_my_ip_i/gtxe2_i/TXOUTCLK=156 drpclk_in=50 gt_refclk1=125 init_clk_in=50 1106 1974 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 2 aurora_8b10b_dup_x4_strm 4 Duplex Streaming X X X X X X X X X X X X 4 3 2 1 GTXQ0 None true true 1 DUT/inst/my_ip_core_i/gt_wrapper_i/my_ip_multi_gt_i/gt2_my_ip_i/gtxe2_i/TXOUTCLK=156 drpclk_in=50 gt_refclk1=125 init_clk_in=50 814 1494 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 2 aurora_8b10b_dup_x8_frm 8 Duplex Framing X X X X X X X X 8 7 6 5 4 3 2 1 GTXQ1 None true true 1 DUT/inst/my_ip_core_i/gt_wrapper_i/my_ip_multi_gt_i/gt4_my_ip_i/gtxe2_i/TXOUTCLK=156 drpclk_in=50 gt_refclk1=125 init_clk_in=50 2256 3422 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 2 aurora_8b10b_dup_x8_strm 8 Duplex Streaming X X X X X X X X 8 7 6 5 4 3 2 1 GTXQ1 None true true 1 DUT/inst/my_ip_core_i/gt_wrapper_i/my_ip_multi_gt_i/gt4_my_ip_i/gtxe2_i/TXOUTCLK=156 drpclk_in=50 gt_refclk1=125 init_clk_in=50 1316 2498 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 2 aurora_8b10b_rx_x16_frm 16 RX-only_Simplex Framing 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 GTXQ1 GTXQ3 true true 1 DUT/inst/my_ip_core_i/gt_wrapper_i/my_ip_multi_gt_i/gt8_my_ip_i/gtxe2_i/TXOUTCLK=156 drpclk_in=50 gt_refclk1=125 gt_refclk2=125 init_clk_in=50 4543 5103 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 2 aurora_8b10b_rx_x16_strm 16 RX-only_Simplex Streaming 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 GTXQ1 GTXQ3 true true 1 DUT/inst/my_ip_core_i/gt_wrapper_i/my_ip_multi_gt_i/gt8_my_ip_i/gtxe2_i/TXOUTCLK=156 drpclk_in=50 gt_refclk1=125 gt_refclk2=125 init_clk_in=50 1565 3269 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 2 aurora_8b10b_rx_x1_frm 1 RX-only_Simplex Framing X X X X X X X X X X X X X X X 1 GTXQ0 None true true 1 DUT/inst/my_ip_core_i/gt_wrapper_i/my_ip_multi_gt_i/gt0_my_ip_i/gtxe2_i/TXOUTCLK=156 drpclk_in=50 gt_refclk1=125 init_clk_in=50 282 498 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 2 aurora_8b10b_rx_x1_strm 1 RX-only_Simplex Streaming X X X X X X X X X X X X X X X 1 GTXQ0 None true true 1 DUT/inst/my_ip_core_i/gt_wrapper_i/my_ip_multi_gt_i/gt0_my_ip_i/gtxe2_i/TXOUTCLK=156 drpclk_in=50 gt_refclk1=125 init_clk_in=50 274 454 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 2 aurora_8b10b_rx_x2_frm 2 RX-only_Simplex Framing X X X X X X X X X X X X X X 2 1 GTXQ0 None true true 1 DUT/inst/my_ip_core_i/gt_wrapper_i/my_ip_multi_gt_i/gt0_my_ip_i/gtxe2_i/TXOUTCLK=156 drpclk_in=50 gt_refclk1=125 init_clk_in=50 456 778 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 2 aurora_8b10b_rx_x2_strm 2 RX-only_Simplex Streaming X X X X X X X X X X X X X X 2 1 GTXQ0 None true true 1 DUT/inst/my_ip_core_i/gt_wrapper_i/my_ip_multi_gt_i/gt0_my_ip_i/gtxe2_i/TXOUTCLK=156 drpclk_in=50 gt_refclk1=125 init_clk_in=50 373 665 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 2 aurora_8b10b_rx_x4_frm 4 RX-only_Simplex Framing X X X X X X X X X X X X 4 3 2 1 GTXQ0 None true true 1 DUT/inst/my_ip_core_i/gt_wrapper_i/my_ip_multi_gt_i/gt2_my_ip_i/gtxe2_i/TXOUTCLK=156 drpclk_in=50 gt_refclk1=125 init_clk_in=50 802 1255 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 2 aurora_8b10b_rx_x4_strm 4 RX-only_Simplex Streaming X X X X X X X X X X X X 4 3 2 1 GTXQ0 None true true 1 DUT/inst/my_ip_core_i/gt_wrapper_i/my_ip_multi_gt_i/gt2_my_ip_i/gtxe2_i/TXOUTCLK=156 drpclk_in=50 gt_refclk1=125 init_clk_in=50 544 1037 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 2 aurora_8b10b_rx_x8_frm 8 RX-only_Simplex Framing X X X X X X X X 8 7 6 5 4 3 2 1 GTXQ1 None true true 1 DUT/inst/my_ip_core_i/gt_wrapper_i/my_ip_multi_gt_i/gt4_my_ip_i/gtxe2_i/TXOUTCLK=156 drpclk_in=50 gt_refclk1=125 init_clk_in=50 1784 2218 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 2 aurora_8b10b_rx_x8_strm 8 RX-only_Simplex Streaming X X X X X X X X 8 7 6 5 4 3 2 1 GTXQ1 None true true 1 DUT/inst/my_ip_core_i/gt_wrapper_i/my_ip_multi_gt_i/gt4_my_ip_i/gtxe2_i/TXOUTCLK=156 drpclk_in=50 gt_refclk1=125 init_clk_in=50 882 1781 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 2 aurora_8b10b_tx_x16_frm 16 TX-only_Simplex Framing 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 GTXQ1 GTXQ3 true true 1 DUT/inst/my_ip_core_i/gt_wrapper_i/my_ip_multi_gt_i/gt8_my_ip_i/gtxe2_i/TXOUTCLK=156 drpclk_in=50 gt_refclk1=125 gt_refclk2=125 init_clk_in=50 973 2545 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 2 aurora_8b10b_tx_x16_strm 16 TX-only_Simplex Streaming 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 GTXQ1 GTXQ3 true true 1 DUT/inst/my_ip_core_i/gt_wrapper_i/my_ip_multi_gt_i/gt8_my_ip_i/gtxe2_i/TXOUTCLK=156 drpclk_in=50 gt_refclk1=125 gt_refclk2=125 init_clk_in=50 881 1609 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 2 aurora_8b10b_tx_x1_frm 1 TX-only_Simplex Framing X X X X X X X X X X X X X X X 1 GTXQ0 None true true 1 DUT/inst/my_ip_core_i/gt_wrapper_i/my_ip_multi_gt_i/gt0_my_ip_i/gtxe2_i/TXOUTCLK=156 drpclk_in=50 gt_refclk1=125 init_clk_in=50 199 410 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 2 aurora_8b10b_tx_x1_strm 1 TX-only_Simplex Streaming X X X X X X X X X X X X X X X 1 GTXQ0 None true true 1 DUT/inst/my_ip_core_i/gt_wrapper_i/my_ip_multi_gt_i/gt0_my_ip_i/gtxe2_i/TXOUTCLK=156 drpclk_in=50 gt_refclk1=125 init_clk_in=50 184 343 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 2 aurora_8b10b_tx_x2_frm 2 TX-only_Simplex Framing X X X X X X X X X X X X X X 2 1 GTXQ0 None true true 1 DUT/inst/my_ip_core_i/gt_wrapper_i/my_ip_multi_gt_i/gt0_my_ip_i/gtxe2_i/TXOUTCLK=156 drpclk_in=50 gt_refclk1=125 init_clk_in=50 251 538 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 2 aurora_8b10b_tx_x2_strm 2 TX-only_Simplex Streaming X X X X X X X X X X X X X X 2 1 GTXQ0 None true true 1 DUT/inst/my_ip_core_i/gt_wrapper_i/my_ip_multi_gt_i/gt0_my_ip_i/gtxe2_i/TXOUTCLK=156 drpclk_in=50 gt_refclk1=125 init_clk_in=50 234 433 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 2 aurora_8b10b_tx_x4_frm 4 TX-only_Simplex Framing X X X X X X X X X X X X 4 3 2 1 GTXQ0 None true true 1 DUT/inst/my_ip_core_i/gt_wrapper_i/my_ip_multi_gt_i/gt2_my_ip_i/gtxe2_i/TXOUTCLK=156 drpclk_in=50 gt_refclk1=125 init_clk_in=50 363 863 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 2 aurora_8b10b_tx_x4_strm 4 TX-only_Simplex Streaming X X X X X X X X X X X X 4 3 2 1 GTXQ0 None true true 1 DUT/inst/my_ip_core_i/gt_wrapper_i/my_ip_multi_gt_i/gt2_my_ip_i/gtxe2_i/TXOUTCLK=156 drpclk_in=50 gt_refclk1=125 init_clk_in=50 324 601 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 2 aurora_8b10b_tx_x8_frm 8 TX-only_Simplex Framing X X X X X X X X 8 7 6 5 4 3 2 1 GTXQ1 None true true 1 DUT/inst/my_ip_core_i/gt_wrapper_i/my_ip_multi_gt_i/gt4_my_ip_i/gtxe2_i/TXOUTCLK=156 drpclk_in=50 gt_refclk1=125 init_clk_in=50 566 1424 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 2 aurora_8b10b_tx_x8_strm 8 TX-only_Simplex Streaming X X X X X X X X 8 7 6 5 4 3 2 1 GTXQ1 None true true 1 DUT/inst/my_ip_core_i/gt_wrapper_i/my_ip_multi_gt_i/gt4_my_ip_i/gtxe2_i/TXOUTCLK=156 drpclk_in=50 gt_refclk1=125 init_clk_in=50 511 937 0 0 0 PRODUCTION 1.12 2017-02-17

COPYRIGHT

Copyright 2023 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Artix, ISE, Kintex, Spartan, Versal, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. Arm is a registered trademark of Arm Limited in the EU and other countries. All other trademarks are the property of their respective owners.

LEGAL INFORMATION: PLEASE READ

The information disclosed to you hereunder (the "Materials") is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of Xilinx's limited warranty, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in such critical applications, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos.