Performance and Resource Utilization for DDS Compiler v6.0

Vivado Design Suite Release 2023.2

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Kintex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
PartsPresent
Channels
Mode_of_Operation
Modulus
Parameter_Entry
Noise_Shaping
Phase_Width
Output_Width
Phase_Increment
Resync
Phase_offset
Optimization_Goal
DSP48_Use
OUTPUT_FORM
PINC1
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7k70t fbv676 1 k7_1_large Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Phase_Dithering 30 17 Fixed false Fixed Speed Maximal Twos_Complement aclk 456 110 242 2 4 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_large_resync Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Phase_Dithering 30 17 Streaming true Fixed Speed Minimal Twos_Complement aclk 456 238 399 0 4 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_ras_fact4 Phase_Generator_and_SIN_COS_LUT 1 Rasterized 12444 Hardware_Parameters None 14 16 Programmable false None Speed Minimal Twos_Complement aclk 456 168 244 0 2 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_ras_prime Phase_Generator_and_SIN_COS_LUT 1 Rasterized 241 Hardware_Parameters None 8 16 Programmable false None Speed Minimal Twos_Complement aclk 456 26 61 0 0 1 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_sfdr110 Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Taylor_Series_Corrected 12 20 Programmable false None Speed Minimal Twos_Complement 101000010001 aclk 456 40 170 3 1 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_sfdr140 Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Taylor_Series_Corrected 25 25 Programmable false None Speed Minimal Twos_Complement aclk 456 88 372 5 1 1 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_sfdr70_of Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters None 12 12 Programmable false None Speed Minimal Twos_Complement 101000010001 aclk 456 65 144 0 0 1 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_sfdr84 Phase_Generator_and_SIN_COS_LUT 1 Standard 9 Hardware_Parameters Taylor_Series_Corrected 12 14 Programmable false None Speed Minimal Twos_Complement 101000010001 aclk 456 40 146 3 0 1 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_taylora Phase_Generator_and_SIN_COS_LUT 1 Standard 9 Hardware_Parameters Taylor_Series_Corrected 20 18 Programmable false None Speed Maximal Twos_Complement aclk 456 32 194 4 0 1 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_taylorb Phase_Generator_and_SIN_COS_LUT 16 Standard 9 Hardware_Parameters Taylor_Series_Corrected 20 18 Programmable false None Speed Maximal Twos_Complement aclk 456 84 215 4 0 1 PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
PartsPresent
Channels
Mode_of_Operation
Modulus
Parameter_Entry
Noise_Shaping
Phase_Width
Output_Width
Phase_Increment
Resync
Phase_offset
Optimization_Goal
DSP48_Use
OUTPUT_FORM
PINC1
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcku025 ffva1156 1 ku_1_large Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Phase_Dithering 30 17 Fixed false Fixed Speed Maximal Twos_Complement aclk 522 105 244 2 4 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_large_resync Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Phase_Dithering 30 17 Streaming true Fixed Speed Minimal Twos_Complement aclk 522 229 399 0 4 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_ras_fact4 Phase_Generator_and_SIN_COS_LUT 1 Rasterized 12444 Hardware_Parameters None 14 16 Programmable false None Speed Minimal Twos_Complement aclk 522 169 246 0 2 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_ras_prime Phase_Generator_and_SIN_COS_LUT 1 Rasterized 241 Hardware_Parameters None 8 16 Programmable false None Speed Minimal Twos_Complement aclk 522 26 61 0 0 1 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_sfdr110 Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Taylor_Series_Corrected 12 20 Programmable false None Speed Minimal Twos_Complement 101000010001 aclk 522 39 170 3 1 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_sfdr140 Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Taylor_Series_Corrected 25 25 Programmable false None Speed Minimal Twos_Complement aclk 522 93 372 5 1 1 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_sfdr70_of Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters None 12 12 Programmable false None Speed Minimal Twos_Complement 101000010001 aclk 522 64 146 0 0 1 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_sfdr84 Phase_Generator_and_SIN_COS_LUT 1 Standard 9 Hardware_Parameters Taylor_Series_Corrected 12 14 Programmable false None Speed Minimal Twos_Complement 101000010001 aclk 522 40 146 3 0 1 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_taylora Phase_Generator_and_SIN_COS_LUT 1 Standard 9 Hardware_Parameters Taylor_Series_Corrected 20 18 Programmable false None Speed Maximal Twos_Complement aclk 522 31 194 4 0 1 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_taylorb Phase_Generator_and_SIN_COS_LUT 16 Standard 9 Hardware_Parameters Taylor_Series_Corrected 20 18 Programmable false None Speed Maximal Twos_Complement aclk 522 79 215 4 0 1 PRODUCTION 1.25 12-04-2018

Kintex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
PartsPresent
Channels
Mode_of_Operation
Modulus
Parameter_Entry
Noise_Shaping
Phase_Width
Output_Width
Phase_Increment
Resync
Phase_offset
Optimization_Goal
DSP48_Use
OUTPUT_FORM
PINC1
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcku11p ffva1156 1 kup_1_large Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Phase_Dithering 30 17 Fixed false Fixed Speed Maximal Twos_Complement aclk 642 105 242 2 4 0 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_large_resync Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Phase_Dithering 30 17 Streaming true Fixed Speed Minimal Twos_Complement aclk 642 227 399 0 4 0 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_ras_fact4 Phase_Generator_and_SIN_COS_LUT 1 Rasterized 12444 Hardware_Parameters None 14 16 Programmable false None Speed Minimal Twos_Complement aclk 642 168 244 0 2 0 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_ras_prime Phase_Generator_and_SIN_COS_LUT 1 Rasterized 241 Hardware_Parameters None 8 16 Programmable false None Speed Minimal Twos_Complement aclk 642 24 61 0 0 1 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_sfdr110 Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Taylor_Series_Corrected 12 20 Programmable false None Speed Minimal Twos_Complement 101000010001 aclk 642 40 170 3 1 0 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_sfdr140 Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Taylor_Series_Corrected 25 25 Programmable false None Speed Minimal Twos_Complement aclk 642 91 372 5 1 1 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_sfdr70_of Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters None 12 12 Programmable false None Speed Minimal Twos_Complement 101000010001 aclk 642 64 144 0 0 1 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_sfdr84 Phase_Generator_and_SIN_COS_LUT 1 Standard 9 Hardware_Parameters Taylor_Series_Corrected 12 14 Programmable false None Speed Minimal Twos_Complement 101000010001 aclk 642 39 146 3 0 1 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_taylora Phase_Generator_and_SIN_COS_LUT 1 Standard 9 Hardware_Parameters Taylor_Series_Corrected 20 18 Programmable false None Speed Maximal Twos_Complement aclk 642 31 194 4 0 1 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_taylorb Phase_Generator_and_SIN_COS_LUT 16 Standard 9 Hardware_Parameters Taylor_Series_Corrected 20 18 Programmable false None Speed Maximal Twos_Complement aclk 642 79 215 4 0 1 PRODUCTION 1.29 05-01-2022

Versal ACAP

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
PartsPresent
Channels
Mode_of_Operation
Modulus
Parameter_Entry
Noise_Shaping
Phase_Width
Output_Width
Phase_Increment
Resync
Phase_offset
Optimization_Goal
DSP48_Use
OUTPUT_FORM
PINC1
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvc1902 vsva2197 1LP ver_1_large Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Phase_Dithering 30 17 Fixed false Fixed Speed Maximal Twos_Complement aclk 615 129 253 2 4 0 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP ver_1_large_resync Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Phase_Dithering 30 17 Streaming true Fixed Speed Minimal Twos_Complement aclk 533 228 433 0 4 0 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP ver_1_ras_fact4 Phase_Generator_and_SIN_COS_LUT 1 Rasterized 12444 Hardware_Parameters None 14 16 Programmable false None Speed Minimal Twos_Complement aclk 582 176 246 0 2 0 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP ver_1_ras_prime Phase_Generator_and_SIN_COS_LUT 1 Rasterized 241 Hardware_Parameters None 8 16 Programmable false None Speed Minimal Twos_Complement aclk 615 35 61 0 0 1 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP ver_1_sfdr110 Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Taylor_Series_Corrected 12 20 Programmable false None Speed Minimal Twos_Complement 101000010001 aclk 615 39 214 3 1 0 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP ver_1_sfdr140 Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Taylor_Series_Corrected 25 25 Programmable false None Speed Minimal Twos_Complement aclk 615 90 446 5 1 1 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP ver_1_sfdr70_of Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters None 12 12 Programmable false None Speed Minimal Twos_Complement 101000010001 aclk 615 62 146 0 0 1 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP ver_1_sfdr84 Phase_Generator_and_SIN_COS_LUT 1 Standard 9 Hardware_Parameters Taylor_Series_Corrected 12 14 Programmable false None Speed Minimal Twos_Complement 101000010001 aclk 615 36 178 3 0 1 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP ver_1_taylora Phase_Generator_and_SIN_COS_LUT 1 Standard 9 Hardware_Parameters Taylor_Series_Corrected 20 18 Programmable false None Speed Maximal Twos_Complement aclk 615 27 194 4 0 1 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP ver_1_taylorb Phase_Generator_and_SIN_COS_LUT 16 Standard 9 Hardware_Parameters Taylor_Series_Corrected 20 18 Programmable false None Speed Maximal Twos_Complement aclk 615 81 215 4 0 1 PRODUCTION 2.12 2023-09-01

Virtex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
PartsPresent
Channels
Mode_of_Operation
Modulus
Parameter_Entry
Noise_Shaping
Phase_Width
Output_Width
Phase_Increment
Resync
Phase_offset
Optimization_Goal
DSP48_Use
OUTPUT_FORM
PINC1
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7vx485t ffg1157 1 v7_1_large Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Phase_Dithering 30 17 Fixed false Fixed Speed Maximal Twos_Complement aclk 456 110 242 2 4 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_large_resync Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Phase_Dithering 30 17 Streaming true Fixed Speed Minimal Twos_Complement aclk 456 238 399 0 4 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_ras_fact4 Phase_Generator_and_SIN_COS_LUT 1 Rasterized 12444 Hardware_Parameters None 14 16 Programmable false None Speed Minimal Twos_Complement aclk 456 168 244 0 2 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_ras_prime Phase_Generator_and_SIN_COS_LUT 1 Rasterized 241 Hardware_Parameters None 8 16 Programmable false None Speed Minimal Twos_Complement aclk 456 26 61 0 0 1 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_sfdr110 Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Taylor_Series_Corrected 12 20 Programmable false None Speed Minimal Twos_Complement 101000010001 aclk 456 40 170 3 1 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_sfdr140 Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Taylor_Series_Corrected 25 25 Programmable false None Speed Minimal Twos_Complement aclk 456 88 372 5 1 1 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_sfdr70_of Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters None 12 12 Programmable false None Speed Minimal Twos_Complement 101000010001 aclk 456 65 144 0 0 1 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_sfdr84 Phase_Generator_and_SIN_COS_LUT 1 Standard 9 Hardware_Parameters Taylor_Series_Corrected 12 14 Programmable false None Speed Minimal Twos_Complement 101000010001 aclk 456 40 146 3 0 1 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_taylora Phase_Generator_and_SIN_COS_LUT 1 Standard 9 Hardware_Parameters Taylor_Series_Corrected 20 18 Programmable false None Speed Maximal Twos_Complement aclk 456 32 194 4 0 1 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_taylorb Phase_Generator_and_SIN_COS_LUT 16 Standard 9 Hardware_Parameters Taylor_Series_Corrected 20 18 Programmable false None Speed Maximal Twos_Complement aclk 456 84 215 4 0 1 PRODUCTION 1.12 2014-09-11

Virtex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
PartsPresent
Channels
Mode_of_Operation
Modulus
Parameter_Entry
Noise_Shaping
Phase_Width
Output_Width
Phase_Increment
Resync
Phase_offset
Optimization_Goal
DSP48_Use
OUTPUT_FORM
PINC1
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu065 ffvc1517 1 vu_1_large Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Phase_Dithering 30 17 Fixed false Fixed Speed Maximal Twos_Complement aclk 522 105 242 2 4 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_large_resync Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Phase_Dithering 30 17 Streaming true Fixed Speed Minimal Twos_Complement aclk 522 232 399 0 4 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_ras_fact4 Phase_Generator_and_SIN_COS_LUT 1 Rasterized 12444 Hardware_Parameters None 14 16 Programmable false None Speed Minimal Twos_Complement aclk 522 168 246 0 2 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_ras_prime Phase_Generator_and_SIN_COS_LUT 1 Rasterized 241 Hardware_Parameters None 8 16 Programmable false None Speed Minimal Twos_Complement aclk 522 25 61 0 0 1 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_sfdr110 Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Taylor_Series_Corrected 12 20 Programmable false None Speed Minimal Twos_Complement 101000010001 aclk 522 39 170 3 1 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_sfdr140 Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Taylor_Series_Corrected 25 25 Programmable false None Speed Minimal Twos_Complement aclk 522 93 372 5 1 1 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_sfdr70_of Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters None 12 12 Programmable false None Speed Minimal Twos_Complement 101000010001 aclk 522 64 146 0 0 1 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_sfdr84 Phase_Generator_and_SIN_COS_LUT 1 Standard 9 Hardware_Parameters Taylor_Series_Corrected 12 14 Programmable false None Speed Minimal Twos_Complement 101000010001 aclk 522 40 146 3 0 1 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_taylora Phase_Generator_and_SIN_COS_LUT 1 Standard 9 Hardware_Parameters Taylor_Series_Corrected 20 18 Programmable false None Speed Maximal Twos_Complement aclk 522 31 194 4 0 1 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_taylorb Phase_Generator_and_SIN_COS_LUT 16 Standard 9 Hardware_Parameters Taylor_Series_Corrected 20 18 Programmable false None Speed Maximal Twos_Complement aclk 522 79 215 4 0 1 PRODUCTION 1.27 12-04-2018

Virtex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
PartsPresent
Channels
Mode_of_Operation
Modulus
Parameter_Entry
Noise_Shaping
Phase_Width
Output_Width
Phase_Increment
Resync
Phase_offset
Optimization_Goal
DSP48_Use
OUTPUT_FORM
PINC1
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu11p flga2577 1 vup_1_large Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Phase_Dithering 30 17 Fixed false Fixed Speed Maximal Twos_Complement aclk 642 105 242 2 4 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_large_resync Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Phase_Dithering 30 17 Streaming true Fixed Speed Minimal Twos_Complement aclk 642 227 399 0 4 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_ras_fact4 Phase_Generator_and_SIN_COS_LUT 1 Rasterized 12444 Hardware_Parameters None 14 16 Programmable false None Speed Minimal Twos_Complement aclk 642 168 244 0 2 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_ras_prime Phase_Generator_and_SIN_COS_LUT 1 Rasterized 241 Hardware_Parameters None 8 16 Programmable false None Speed Minimal Twos_Complement aclk 642 24 61 0 0 1 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_sfdr110 Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Taylor_Series_Corrected 12 20 Programmable false None Speed Minimal Twos_Complement 101000010001 aclk 642 39 170 3 1 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_sfdr140 Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Taylor_Series_Corrected 25 25 Programmable false None Speed Minimal Twos_Complement aclk 642 91 372 5 1 1 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_sfdr70_of Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters None 12 12 Programmable false None Speed Minimal Twos_Complement 101000010001 aclk 642 64 144 0 0 1 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_sfdr84 Phase_Generator_and_SIN_COS_LUT 1 Standard 9 Hardware_Parameters Taylor_Series_Corrected 12 14 Programmable false None Speed Minimal Twos_Complement 101000010001 aclk 642 39 146 3 0 1 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_taylora Phase_Generator_and_SIN_COS_LUT 1 Standard 9 Hardware_Parameters Taylor_Series_Corrected 20 18 Programmable false None Speed Maximal Twos_Complement aclk 642 31 194 4 0 1 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_taylorb Phase_Generator_and_SIN_COS_LUT 16 Standard 9 Hardware_Parameters Taylor_Series_Corrected 20 18 Programmable false None Speed Maximal Twos_Complement aclk 642 78 215 4 0 1 PRODUCTION 1.28 03-30-2022

Zynq UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
PartsPresent
Channels
Mode_of_Operation
Modulus
Parameter_Entry
Noise_Shaping
Phase_Width
Output_Width
Phase_Increment
Resync
Phase_offset
Optimization_Goal
DSP48_Use
OUTPUT_FORM
PINC1
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xczu9eg ffvb1156 1LV zup_1_large Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Phase_Dithering 30 17 Fixed false Fixed Speed Maximal Twos_Complement aclk 516 85 242 2 4 0 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_large_resync Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Phase_Dithering 30 17 Streaming true Fixed Speed Minimal Twos_Complement aclk 516 204 399 0 4 0 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_ras_fact4 Phase_Generator_and_SIN_COS_LUT 1 Rasterized 12444 Hardware_Parameters None 14 16 Programmable false None Speed Minimal Twos_Complement aclk 516 158 244 0 2 0 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_ras_prime Phase_Generator_and_SIN_COS_LUT 1 Rasterized 241 Hardware_Parameters None 8 16 Programmable false None Speed Minimal Twos_Complement aclk 516 24 61 0 0 1 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_sfdr110 Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Taylor_Series_Corrected 12 20 Programmable false None Speed Minimal Twos_Complement 101000010001 aclk 516 40 170 3 1 0 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_sfdr140 Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Taylor_Series_Corrected 25 25 Programmable false None Speed Minimal Twos_Complement aclk 516 88 372 5 1 1 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_sfdr70_of Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters None 12 12 Programmable false None Speed Minimal Twos_Complement 101000010001 aclk 516 60 144 0 0 1 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_sfdr84 Phase_Generator_and_SIN_COS_LUT 1 Standard 9 Hardware_Parameters Taylor_Series_Corrected 12 14 Programmable false None Speed Minimal Twos_Complement 101000010001 aclk 516 39 146 3 0 1 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_taylora Phase_Generator_and_SIN_COS_LUT 1 Standard 9 Hardware_Parameters Taylor_Series_Corrected 20 18 Programmable false None Speed Maximal Twos_Complement aclk 516 31 194 4 0 1 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_taylorb Phase_Generator_and_SIN_COS_LUT 16 Standard 9 Hardware_Parameters Taylor_Series_Corrected 20 18 Programmable false None Speed Maximal Twos_Complement aclk 516 76 235 4 0 1 PRODUCTION 1.30 05-15-2022

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