Resource Utilization for High Speed SelectIO Wizard v3.6

Vivado Design Suite Release 2020.2

Interpreting the results

This page contains resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Virtex UltraScale

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
PRESET
BUS_DIR
PLL0_DATA_SPEED
PLL0_RX_EXTERNAL_CLK_TO_DATA
PLL0_CLK_SOURCE
SERIALIZATION_FACTOR
ENABLE_RIU_INTERFACE
ENABLE_BITSLIP
BYTE0_PIN0_BUS_DIR
BYTE0_PIN1_BUS_DIR
BYTE0_PIN2_BUS_DIR
BYTE0_PIN3_BUS_DIR
BYTE0_PIN4_BUS_DIR
BYTE0_PIN5_BUS_DIR
BYTE0_PIN6_BUS_DIR
BYTE0_PIN7_BUS_DIR
BYTE0_PIN8_BUS_DIR
BYTE0_PIN9_BUS_DIR
BYTE0_PIN10_BUS_DIR
BYTE0_PIN11_BUS_DIR
BYTE0_PIN12_BUS_DIR
BYTE0_PIN0_DATA_STROBE
BYTE0_PIN1_DATA_STROBE
BYTE0_PIN2_DATA_STROBE
BYTE0_PIN3_DATA_STROBE
BYTE0_PIN4_DATA_STROBE
BYTE0_PIN5_DATA_STROBE
BYTE0_PIN6_DATA_STROBE
BYTE0_PIN7_DATA_STROBE
BYTE0_PIN8_DATA_STROBE
BYTE0_PIN9_DATA_STROBE
BYTE0_PIN10_DATA_STROBE
BYTE0_PIN11_DATA_STROBE
BYTE0_PIN12_DATA_STROBE
BYTE0_PIN0_SIG_TYPE
BYTE0_PIN1_SIG_TYPE
BYTE0_PIN2_SIG_TYPE
BYTE0_PIN3_SIG_TYPE
BYTE0_PIN4_SIG_TYPE
BYTE0_PIN5_SIG_TYPE
BYTE0_PIN6_SIG_TYPE
BYTE0_PIN7_SIG_TYPE
BYTE0_PIN8_SIG_TYPE
BYTE0_PIN9_SIG_TYPE
BYTE0_PIN10_SIG_TYPE
BYTE0_PIN11_SIG_TYPE
BYTE0_PIN12_SIG_TYPE
ENABLE_BYTE0_PIN0
ENABLE_BYTE0_PIN1
ENABLE_BYTE0_PIN2
ENABLE_BYTE0_PIN3
ENABLE_BYTE0_PIN4
ENABLE_BYTE0_PIN5
ENABLE_BYTE0_PIN6
ENABLE_BYTE0_PIN7
ENABLE_BYTE0_PIN8
ENABLE_BYTE0_PIN9
ENABLE_BYTE0_PIN10
ENABLE_BYTE0_PIN11
ENABLE_BYTE0_PIN12
ENABLE_BYTE1_PIN0
ENABLE_BYTE1_PIN1
ENABLE_BYTE1_PIN2
ENABLE_BYTE1_PIN3
ENABLE_BYTE1_PIN4
ENABLE_BYTE1_PIN5
ENABLE_BYTE1_PIN6
ENABLE_BYTE1_PIN7
ENABLE_BYTE1_PIN8
ENABLE_BYTE1_PIN9
ENABLE_BYTE1_PIN10
ENABLE_BYTE1_PIN11
ENABLE_BYTE1_PIN12
BYTE1_PIN0_BUS_DIR
BYTE1_PIN1_BUS_DIR
BYTE1_PIN2_BUS_DIR
BYTE1_PIN3_BUS_DIR
BYTE1_PIN4_BUS_DIR
BYTE1_PIN5_BUS_DIR
BYTE1_PIN6_BUS_DIR
BYTE1_PIN7_BUS_DIR
BYTE1_PIN8_BUS_DIR
BYTE1_PIN9_BUS_DIR
BYTE1_PIN10_BUS_DIR
BYTE1_PIN11_BUS_DIR
BYTE1_PIN12_BUS_DIR
BYTE1_PIN0_SIG_TYPE
BYTE1_PIN1_SIG_TYPE
BYTE1_PIN2_SIG_TYPE
BYTE1_PIN3_SIG_TYPE
BYTE1_PIN4_SIG_TYPE
BYTE1_PIN5_SIG_TYPE
BYTE1_PIN6_SIG_TYPE
BYTE1_PIN7_SIG_TYPE
BYTE1_PIN8_SIG_TYPE
BYTE1_PIN9_SIG_TYPE
BYTE1_PIN10_SIG_TYPE
BYTE1_PIN11_SIG_TYPE
BYTE1_PIN12_SIG_TYPE
BYTE1_PIN0_DATA_STROBE
BYTE1_PIN1_DATA_STROBE
BYTE1_PIN2_DATA_STROBE
BYTE1_PIN3_DATA_STROBE
BYTE1_PIN4_DATA_STROBE
BYTE1_PIN5_DATA_STROBE
BYTE1_PIN6_DATA_STROBE
BYTE1_PIN7_DATA_STROBE
BYTE1_PIN8_DATA_STROBE
BYTE1_PIN9_DATA_STROBE
BYTE1_PIN10_DATA_STROBE
BYTE1_PIN11_DATA_STROBE
BYTE1_PIN12_DATA_STROBE
ENABLE_BYTE2_PIN0
ENABLE_BYTE2_PIN1
ENABLE_BYTE2_PIN2
ENABLE_BYTE2_PIN3
ENABLE_BYTE2_PIN4
ENABLE_BYTE2_PIN5
ENABLE_BYTE2_PIN6
ENABLE_BYTE2_PIN7
ENABLE_BYTE2_PIN8
ENABLE_BYTE2_PIN9
ENABLE_BYTE2_PIN10
ENABLE_BYTE2_PIN11
ENABLE_BYTE2_PIN12
BYTE2_PIN0_BUS_DIR
BYTE2_PIN1_BUS_DIR
BYTE2_PIN2_BUS_DIR
BYTE2_PIN3_BUS_DIR
BYTE2_PIN4_BUS_DIR
BYTE2_PIN5_BUS_DIR
BYTE2_PIN6_BUS_DIR
BYTE2_PIN7_BUS_DIR
BYTE2_PIN8_BUS_DIR
BYTE2_PIN9_BUS_DIR
BYTE2_PIN10_BUS_DIR
BYTE2_PIN11_BUS_DIR
BYTE2_PIN12_BUS_DIR
BYTE2_PIN0_SIG_TYPE
BYTE2_PIN1_SIG_TYPE
BYTE2_PIN2_SIG_TYPE
BYTE2_PIN3_SIG_TYPE
BYTE2_PIN4_SIG_TYPE
BYTE2_PIN5_SIG_TYPE
BYTE2_PIN6_SIG_TYPE
BYTE2_PIN7_SIG_TYPE
BYTE2_PIN8_SIG_TYPE
BYTE2_PIN9_SIG_TYPE
BYTE2_PIN10_SIG_TYPE
BYTE2_PIN11_SIG_TYPE
BYTE2_PIN12_SIG_TYPE
BYTE2_PIN0_DATA_STROBE
BYTE2_PIN1_DATA_STROBE
BYTE2_PIN2_DATA_STROBE
BYTE2_PIN3_DATA_STROBE
BYTE2_PIN4_DATA_STROBE
BYTE2_PIN5_DATA_STROBE
BYTE2_PIN6_DATA_STROBE
BYTE2_PIN7_DATA_STROBE
BYTE2_PIN8_DATA_STROBE
BYTE2_PIN9_DATA_STROBE
BYTE2_PIN10_DATA_STROBE
BYTE2_PIN11_DATA_STROBE
BYTE2_PIN12_DATA_STROBE
ENABLE_BYTE3_PIN0
ENABLE_BYTE3_PIN1
ENABLE_BYTE3_PIN2
ENABLE_BYTE3_PIN3
ENABLE_BYTE3_PIN4
ENABLE_BYTE3_PIN5
ENABLE_BYTE3_PIN6
ENABLE_BYTE3_PIN7
ENABLE_BYTE3_PIN8
ENABLE_BYTE3_PIN9
ENABLE_BYTE3_PIN10
ENABLE_BYTE3_PIN11
ENABLE_BYTE3_PIN12
BYTE3_PIN0_BUS_DIR
BYTE3_PIN1_BUS_DIR
BYTE3_PIN2_BUS_DIR
BYTE3_PIN3_BUS_DIR
BYTE3_PIN4_BUS_DIR
BYTE3_PIN5_BUS_DIR
BYTE3_PIN6_BUS_DIR
BYTE3_PIN7_BUS_DIR
BYTE3_PIN8_BUS_DIR
BYTE3_PIN9_BUS_DIR
BYTE3_PIN10_BUS_DIR
BYTE3_PIN11_BUS_DIR
BYTE3_PIN12_BUS_DIR
BYTE3_PIN0_SIG_TYPE
BYTE3_PIN1_SIG_TYPE
BYTE3_PIN2_SIG_TYPE
BYTE3_PIN3_SIG_TYPE
BYTE3_PIN4_SIG_TYPE
BYTE3_PIN5_SIG_TYPE
BYTE3_PIN6_SIG_TYPE
BYTE3_PIN7_SIG_TYPE
BYTE3_PIN8_SIG_TYPE
BYTE3_PIN9_SIG_TYPE
BYTE3_PIN10_SIG_TYPE
BYTE3_PIN11_SIG_TYPE
BYTE3_PIN12_SIG_TYPE
BYTE3_PIN0_DATA_STROBE
BYTE3_PIN1_DATA_STROBE
BYTE3_PIN2_DATA_STROBE
BYTE3_PIN3_DATA_STROBE
BYTE3_PIN4_DATA_STROBE
BYTE3_PIN5_DATA_STROBE
BYTE3_PIN6_DATA_STROBE
BYTE3_PIN7_DATA_STROBE
BYTE3_PIN8_DATA_STROBE
BYTE3_PIN9_DATA_STROBE
BYTE3_PIN10_DATA_STROBE
BYTE3_PIN11_DATA_STROBE
BYTE3_PIN12_DATA_STROBE
Fixed clocks (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu065 ffvc1517 -3 bidir_bus_dir__conf_char1 None 2 1400.000 4 BUFG_TO_PLL 8 0 1 BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR Strobe Data Data Data Data Data Strobe Data Data Data Data Data Data SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE true true true true true true true true true true true true true true true true true true true true true true true true true true BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE Strobe Data Data Data Data Data Strobe Data Data Data Data Data Data true true true true true true true true true true true true true BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE Strobe Data Data Data Data Data Strobe Data Data Data Data Data Data true true true true true true true true true true true true true BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE Strobe Data Data Data Data Data Strobe Data Data Data Data Data Data clk=500 fifo_rd_clk_0=175 fifo_rd_clk_1=175 fifo_rd_clk_10=175 fifo_rd_clk_11=175 fifo_rd_clk_12=175 fifo_rd_clk_13=175 fifo_rd_clk_14=175 fifo_rd_clk_15=175 fifo_rd_clk_16=175 fifo_rd_clk_17=175 fifo_rd_clk_18=175 fifo_rd_clk_19=175 fifo_rd_clk_2=175 fifo_rd_clk_20=175 fifo_rd_clk_21=175 fifo_rd_clk_22=175 fifo_rd_clk_23=175 fifo_rd_clk_24=175 fifo_rd_clk_25=175 fifo_rd_clk_26=175 fifo_rd_clk_27=175 fifo_rd_clk_28=175 fifo_rd_clk_29=175 fifo_rd_clk_3=175 fifo_rd_clk_30=175 fifo_rd_clk_31=175 fifo_rd_clk_32=175 fifo_rd_clk_33=175 fifo_rd_clk_34=175 fifo_rd_clk_35=175 fifo_rd_clk_36=175 fifo_rd_clk_37=175 fifo_rd_clk_38=175 fifo_rd_clk_39=175 fifo_rd_clk_4=175 fifo_rd_clk_40=175 fifo_rd_clk_41=175 fifo_rd_clk_42=175 fifo_rd_clk_43=175 fifo_rd_clk_44=175 fifo_rd_clk_45=175 fifo_rd_clk_46=175 fifo_rd_clk_47=175 fifo_rd_clk_48=175 fifo_rd_clk_49=175 fifo_rd_clk_5=175 fifo_rd_clk_50=175 fifo_rd_clk_51=175 fifo_rd_clk_6=175 fifo_rd_clk_7=175 fifo_rd_clk_8=175 fifo_rd_clk_9=175 riu_clk=200 2167 3149 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 -3 bidir_bus_dir__conf_char2 None 2 1400.000 4 BUFG_TO_PLL 8 0 0 BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR Strobe Data Data Data Data Data Strobe Data Data Data Data Data Data SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE true true true true true true true true true true true true true true true true true true true true true true true true true true BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE Strobe Data Data Data Data Data Strobe Data Data Data Data Data Data true true true true true true true true true true true true true BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE Strobe Data Data Data Data Data Strobe Data Data Data Data Data Data true true true true true true true true true true true true true BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE Strobe Data Data Data Data Data Strobe Data Data Data Data Data Data clk=500 fifo_rd_clk_0=175 fifo_rd_clk_1=175 fifo_rd_clk_10=175 fifo_rd_clk_11=175 fifo_rd_clk_12=175 fifo_rd_clk_13=175 fifo_rd_clk_14=175 fifo_rd_clk_15=175 fifo_rd_clk_16=175 fifo_rd_clk_17=175 fifo_rd_clk_18=175 fifo_rd_clk_19=175 fifo_rd_clk_2=175 fifo_rd_clk_20=175 fifo_rd_clk_21=175 fifo_rd_clk_22=175 fifo_rd_clk_23=175 fifo_rd_clk_24=175 fifo_rd_clk_25=175 fifo_rd_clk_26=175 fifo_rd_clk_27=175 fifo_rd_clk_28=175 fifo_rd_clk_29=175 fifo_rd_clk_3=175 fifo_rd_clk_30=175 fifo_rd_clk_31=175 fifo_rd_clk_32=175 fifo_rd_clk_33=175 fifo_rd_clk_34=175 fifo_rd_clk_35=175 fifo_rd_clk_36=175 fifo_rd_clk_37=175 fifo_rd_clk_38=175 fifo_rd_clk_39=175 fifo_rd_clk_4=175 fifo_rd_clk_40=175 fifo_rd_clk_41=175 fifo_rd_clk_42=175 fifo_rd_clk_43=175 fifo_rd_clk_44=175 fifo_rd_clk_45=175 fifo_rd_clk_46=175 fifo_rd_clk_47=175 fifo_rd_clk_48=175 fifo_rd_clk_49=175 fifo_rd_clk_5=175 fifo_rd_clk_50=175 fifo_rd_clk_51=175 fifo_rd_clk_6=175 fifo_rd_clk_7=175 fifo_rd_clk_8=175 fifo_rd_clk_9=175 riu_clk=200 68 213 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 -3 bidir_bus_dir__conf_char3 None 2 1300.000 4 BUFG_TO_PLL 4 0 1 BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR Strobe Data Data Data Data Data Strobe Data Data Data Data Data Data SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE true true true true true true true true true true true true true true true true true true true true true true true true true true BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE Strobe Data Data Data Data Data Strobe Data Data Data Data Data Data true true true true true true true true true true true true true BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE Strobe Data Data Data Data Data Strobe Data Data Data Data Data Data true true true true true true true true true true true true true BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE Strobe Data Data Data Data Data Strobe Data Data Data Data Data Data clk=500 fifo_rd_clk_0=325 fifo_rd_clk_1=325 fifo_rd_clk_10=325 fifo_rd_clk_11=325 fifo_rd_clk_12=325 fifo_rd_clk_13=325 fifo_rd_clk_14=325 fifo_rd_clk_15=325 fifo_rd_clk_16=325 fifo_rd_clk_17=325 fifo_rd_clk_18=325 fifo_rd_clk_19=325 fifo_rd_clk_2=325 fifo_rd_clk_20=325 fifo_rd_clk_21=325 fifo_rd_clk_22=325 fifo_rd_clk_23=325 fifo_rd_clk_24=325 fifo_rd_clk_25=325 fifo_rd_clk_26=325 fifo_rd_clk_27=325 fifo_rd_clk_28=325 fifo_rd_clk_29=325 fifo_rd_clk_3=325 fifo_rd_clk_30=325 fifo_rd_clk_31=325 fifo_rd_clk_32=325 fifo_rd_clk_33=325 fifo_rd_clk_34=325 fifo_rd_clk_35=325 fifo_rd_clk_36=325 fifo_rd_clk_37=325 fifo_rd_clk_38=325 fifo_rd_clk_39=325 fifo_rd_clk_4=325 fifo_rd_clk_40=325 fifo_rd_clk_41=325 fifo_rd_clk_42=325 fifo_rd_clk_43=325 fifo_rd_clk_44=325 fifo_rd_clk_45=325 fifo_rd_clk_46=325 fifo_rd_clk_47=325 fifo_rd_clk_48=325 fifo_rd_clk_49=325 fifo_rd_clk_5=325 fifo_rd_clk_50=325 fifo_rd_clk_51=325 fifo_rd_clk_6=325 fifo_rd_clk_7=325 fifo_rd_clk_8=325 fifo_rd_clk_9=325 riu_clk=200 991 2129 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 -3 bidir_bus_dir__conf_char4 None 2 1400.000 4 BUFG_TO_PLL 8 0 0 BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR Strobe Data Data Data Data Data Strobe Data Data Data Data Data Data SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE true true true true true true true true true true true true true true true true true true true true true true true true true true BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE Strobe Data Data Data Data Data Strobe Data Data Data Data Data Data true true true true true true true true true true true true true BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE Strobe Data Data Data Data Data Strobe Data Data Data Data Data Data true true true true true true true true true true true true true BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE Strobe Data Data Data Data Data Strobe Data Data Data Data Data Data clk=500 fifo_rd_clk_0=175 fifo_rd_clk_1=175 fifo_rd_clk_10=175 fifo_rd_clk_11=175 fifo_rd_clk_12=175 fifo_rd_clk_13=175 fifo_rd_clk_14=175 fifo_rd_clk_15=175 fifo_rd_clk_16=175 fifo_rd_clk_17=175 fifo_rd_clk_18=175 fifo_rd_clk_19=175 fifo_rd_clk_2=175 fifo_rd_clk_20=175 fifo_rd_clk_21=175 fifo_rd_clk_22=175 fifo_rd_clk_23=175 fifo_rd_clk_24=175 fifo_rd_clk_25=175 fifo_rd_clk_26=175 fifo_rd_clk_27=175 fifo_rd_clk_28=175 fifo_rd_clk_29=175 fifo_rd_clk_3=175 fifo_rd_clk_30=175 fifo_rd_clk_31=175 fifo_rd_clk_32=175 fifo_rd_clk_33=175 fifo_rd_clk_34=175 fifo_rd_clk_35=175 fifo_rd_clk_36=175 fifo_rd_clk_37=175 fifo_rd_clk_38=175 fifo_rd_clk_39=175 fifo_rd_clk_4=175 fifo_rd_clk_40=175 fifo_rd_clk_41=175 fifo_rd_clk_42=175 fifo_rd_clk_43=175 fifo_rd_clk_44=175 fifo_rd_clk_45=175 fifo_rd_clk_46=175 fifo_rd_clk_47=175 fifo_rd_clk_48=175 fifo_rd_clk_49=175 fifo_rd_clk_5=175 fifo_rd_clk_50=175 fifo_rd_clk_51=175 fifo_rd_clk_6=175 fifo_rd_clk_7=175 fifo_rd_clk_8=175 fifo_rd_clk_9=175 riu_clk=200 68 213 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 -3 bidir_bus_dir__conf_char5 None 2 1300.000 4 BUFG_TO_PLL 4 0 0 BIDIR BIDIR Strobe Data SINGLE SINGLE true true false false clk=500 fifo_rd_clk_0=325 fifo_rd_clk_1=325 riu_clk=200 60 63 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 -3 bidir_bus_dir__conf_char6 None 2 1300.000 4 BUFG_TO_PLL 4 0 1 BIDIR BIDIR Strobe Data SINGLE SINGLE true true false false clk=500 fifo_rd_clk_0=325 fifo_rd_clk_1=325 riu_clk=200 83 118 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 -3 bidir_bus_dir__conf_char7 None 2 1400.000 4 BUFG_TO_PLL 8 0 1 BIDIR BIDIR Strobe Data SINGLE SINGLE true true false false clk=500 fifo_rd_clk_0=175 fifo_rd_clk_1=175 riu_clk=200 116 151 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 -3 bidir_bus_dir__conf_char8 None 2 1400.000 4 BUFG_TO_PLL 8 0 0 BIDIR BIDIR Strobe Data SINGLE SINGLE true true false false clk=500 fifo_rd_clk_0=175 fifo_rd_clk_1=175 riu_clk=200 60 63 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 -3 rx_bus_dir__conf_char1 None 1 1300.000 2 BUFG_TO_PLL 8 0 1 RX RX RX RX RX Data Data Data Data Data true true true true true true true true true true true RX RX RX RX RX Data Data Data Data Data true true true true true RX RX RX RX RX RX Data Data Data Data Data Data true true true true true RX RX RX RX RX RX Data Data Data Data Data Data clk=500 fifo_rd_clk_0=163 fifo_rd_clk_1=163 fifo_rd_clk_10=163 fifo_rd_clk_11=163 fifo_rd_clk_13=163 fifo_rd_clk_14=163 fifo_rd_clk_15=163 fifo_rd_clk_16=163 fifo_rd_clk_17=163 fifo_rd_clk_18=163 fifo_rd_clk_2=163 fifo_rd_clk_21=163 fifo_rd_clk_22=163 fifo_rd_clk_23=163 fifo_rd_clk_24=163 fifo_rd_clk_26=163 fifo_rd_clk_27=163 fifo_rd_clk_28=163 fifo_rd_clk_29=163 fifo_rd_clk_3=163 fifo_rd_clk_30=163 fifo_rd_clk_31=163 fifo_rd_clk_32=163 fifo_rd_clk_33=163 fifo_rd_clk_34=163 fifo_rd_clk_35=163 fifo_rd_clk_36=163 fifo_rd_clk_37=163 fifo_rd_clk_4=163 fifo_rd_clk_41=163 fifo_rd_clk_42=163 fifo_rd_clk_43=163 fifo_rd_clk_44=163 fifo_rd_clk_45=163 fifo_rd_clk_46=163 fifo_rd_clk_47=163 fifo_rd_clk_48=163 fifo_rd_clk_49=163 fifo_rd_clk_5=163 fifo_rd_clk_50=163 fifo_rd_clk_6=163 fifo_rd_clk_7=163 riu_clk=200 2004 2790 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 -3 rx_bus_dir__conf_char2 None 1 1300.000 2 BUFG_TO_PLL 8 0 0 RX RX RX RX RX RX Data Data Data Data Data Data true true true true true true true true true true true true RX RX RX RX RX RX Data Data Data Data Data Data true true true true true RX RX RX RX RX RX Data Data Data Data Data Data true true true true true RX RX RX RX RX RX Data Data Data Data Data Data clk=500 fifo_rd_clk_0=163 fifo_rd_clk_1=163 fifo_rd_clk_10=163 fifo_rd_clk_11=163 fifo_rd_clk_13=163 fifo_rd_clk_14=163 fifo_rd_clk_15=163 fifo_rd_clk_16=163 fifo_rd_clk_17=163 fifo_rd_clk_18=163 fifo_rd_clk_19=163 fifo_rd_clk_2=163 fifo_rd_clk_20=163 fifo_rd_clk_21=163 fifo_rd_clk_22=163 fifo_rd_clk_23=163 fifo_rd_clk_24=163 fifo_rd_clk_26=163 fifo_rd_clk_27=163 fifo_rd_clk_28=163 fifo_rd_clk_29=163 fifo_rd_clk_3=163 fifo_rd_clk_30=163 fifo_rd_clk_31=163 fifo_rd_clk_32=163 fifo_rd_clk_33=163 fifo_rd_clk_34=163 fifo_rd_clk_35=163 fifo_rd_clk_36=163 fifo_rd_clk_37=163 fifo_rd_clk_4=163 fifo_rd_clk_41=163 fifo_rd_clk_42=163 fifo_rd_clk_43=163 fifo_rd_clk_44=163 fifo_rd_clk_45=163 fifo_rd_clk_46=163 fifo_rd_clk_47=163 fifo_rd_clk_48=163 fifo_rd_clk_49=163 fifo_rd_clk_5=163 fifo_rd_clk_50=163 fifo_rd_clk_6=163 fifo_rd_clk_7=163 fifo_rd_clk_8=163 fifo_rd_clk_9=163 riu_clk=200 48 195 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 -3 rx_bus_dir__conf_char3 None 1 1300.000 2 BUFG_TO_PLL 4 0 1 RX RX RX RX RX RX Data Data Data Data Data Data true true true true true true true true true true true true RX RX RX RX RX RX Data Data Data Data Data Data true true true true true RX RX RX RX RX RX Data Data Data Data Data Data true true true true true RX RX RX RX RX RX Data Data Data Data Data Data clk=500 fifo_rd_clk_0=325 fifo_rd_clk_1=325 fifo_rd_clk_10=325 fifo_rd_clk_11=325 fifo_rd_clk_13=325 fifo_rd_clk_14=325 fifo_rd_clk_15=325 fifo_rd_clk_16=325 fifo_rd_clk_17=325 fifo_rd_clk_18=325 fifo_rd_clk_19=325 fifo_rd_clk_2=325 fifo_rd_clk_20=325 fifo_rd_clk_21=325 fifo_rd_clk_22=325 fifo_rd_clk_23=325 fifo_rd_clk_24=325 fifo_rd_clk_26=325 fifo_rd_clk_27=325 fifo_rd_clk_28=325 fifo_rd_clk_29=325 fifo_rd_clk_3=325 fifo_rd_clk_30=325 fifo_rd_clk_31=325 fifo_rd_clk_32=325 fifo_rd_clk_33=325 fifo_rd_clk_34=325 fifo_rd_clk_35=325 fifo_rd_clk_36=325 fifo_rd_clk_37=325 fifo_rd_clk_4=325 fifo_rd_clk_41=325 fifo_rd_clk_42=325 fifo_rd_clk_43=325 fifo_rd_clk_44=325 fifo_rd_clk_45=325 fifo_rd_clk_46=325 fifo_rd_clk_47=325 fifo_rd_clk_48=325 fifo_rd_clk_49=325 fifo_rd_clk_5=325 fifo_rd_clk_50=325 fifo_rd_clk_6=325 fifo_rd_clk_7=325 fifo_rd_clk_8=325 fifo_rd_clk_9=325 riu_clk=200 990 2081 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 -3 rx_bus_dir__conf_char4 None 1 1300.000 2 BUFG_TO_PLL 8 0 0 RX RX RX RX RX RX Data Data Data Data Data Data true true true true true true true true true true true true RX RX RX RX RX RX Data Data Data Data Data Data true true true true true RX RX RX RX RX RX Data Data Data Data Data Data true true true true true RX RX RX RX RX RX Data Data Data Data Data Data clk=500 fifo_rd_clk_0=163 fifo_rd_clk_1=163 fifo_rd_clk_10=163 fifo_rd_clk_11=163 fifo_rd_clk_13=163 fifo_rd_clk_14=163 fifo_rd_clk_15=163 fifo_rd_clk_16=163 fifo_rd_clk_17=163 fifo_rd_clk_18=163 fifo_rd_clk_19=163 fifo_rd_clk_2=163 fifo_rd_clk_20=163 fifo_rd_clk_21=163 fifo_rd_clk_22=163 fifo_rd_clk_23=163 fifo_rd_clk_24=163 fifo_rd_clk_26=163 fifo_rd_clk_27=163 fifo_rd_clk_28=163 fifo_rd_clk_29=163 fifo_rd_clk_3=163 fifo_rd_clk_30=163 fifo_rd_clk_31=163 fifo_rd_clk_32=163 fifo_rd_clk_33=163 fifo_rd_clk_34=163 fifo_rd_clk_35=163 fifo_rd_clk_36=163 fifo_rd_clk_37=163 fifo_rd_clk_4=163 fifo_rd_clk_41=163 fifo_rd_clk_42=163 fifo_rd_clk_43=163 fifo_rd_clk_44=163 fifo_rd_clk_45=163 fifo_rd_clk_46=163 fifo_rd_clk_47=163 fifo_rd_clk_48=163 fifo_rd_clk_49=163 fifo_rd_clk_5=163 fifo_rd_clk_50=163 fifo_rd_clk_6=163 fifo_rd_clk_7=163 fifo_rd_clk_8=163 fifo_rd_clk_9=163 riu_clk=200 48 195 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 -3 rx_bus_dir__conf_char5 None 1 1300.000 2 BUFG_TO_PLL 8 0 1 RX Data true clk=500 fifo_rd_clk_0=163 fifo_rd_clk_1=163 fifo_rd_clk_26=163 fifo_rd_clk_27=163 riu_clk=200 240 314 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 -3 rx_bus_dir__conf_char6 None 1 1300.000 2 BUFG_TO_PLL 8 0 0 RX Data true clk=500 fifo_rd_clk_0=163 fifo_rd_clk_1=163 fifo_rd_clk_26=163 fifo_rd_clk_27=163 riu_clk=200 47 66 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 -3 rx_bus_dir__conf_char7 None 1 1300.000 2 BUFG_TO_PLL 4 0 1 RX Data true clk=500 fifo_rd_clk_0=325 fifo_rd_clk_1=325 fifo_rd_clk_26=325 fifo_rd_clk_27=325 riu_clk=200 128 230 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 -3 rx_bus_dir__conf_char8 None 1 1300.000 2 BUFG_TO_PLL 4 0 0 RX Data true clk=500 fifo_rd_clk_0=325 fifo_rd_clk_1=325 fifo_rd_clk_26=325 fifo_rd_clk_27=325 riu_clk=200 47 66 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 -3 tx_bus_dir__conf_char1 None 0 1400.000 BUFG_TO_PLL 8 0 TX TX TX TX TX TX TX TX TX TX TX TX TX Data Data Data Data Data Data Data Data Data Data Data Data Data SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE true true true true true true true true true true true true true true true true true true true true true true true true true true TX TX TX TX TX TX TX TX TX TX TX TX TX SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE Data Data Data Data Data Data Data Data Data Data Data Data Data true true true true true true true true true true true true true TX TX TX TX TX TX TX TX TX TX TX TX TX SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE Data Data Data Data Data Data Data Data Data Data Data Data Data true true true true true true true true true true true true true TX TX TX TX TX TX TX TX TX TX TX TX TX SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE Data Data Data Data Data Data Data Data Data Data Data Data Data clk=500 riu_clk=200 68 247 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 -3 tx_bus_dir__conf_char2 None 0 1300.000 BUFG_TO_PLL 4 0 TX TX TX TX TX TX TX TX TX TX TX TX TX Data Data Data Data Data Data Data Data Data Data Data Data Data SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE true true true true true true true true true true true true true true true true true true true true true true true true true true TX TX TX TX TX TX TX TX TX TX TX TX TX SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE Data Data Data Data Data Data Data Data Data Data Data Data Data true true true true true true true true true true true true true TX TX TX TX TX TX TX TX TX TX TX TX TX SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE Data Data Data Data Data Data Data Data Data Data Data Data Data true true true true true true true true true true true true true TX TX TX TX TX TX TX TX TX TX TX TX TX SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE Data Data Data Data Data Data Data Data Data Data Data Data Data clk=500 riu_clk=200 68 247 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 -3 tx_bus_dir__conf_char3 None 0 1400.000 BUFG_TO_PLL 8 0 TX Data true clk=500 riu_clk=200 64 80 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 -3 tx_bus_dir__conf_char4 None 0 1300.000 BUFG_TO_PLL 4 0 TX Data true clk=500 riu_clk=200 63 80 0 0 0 PRODUCTION 1.27 12-04-2018

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