Performance and Resource Utilization for IEEE 802.3 Clause 74 FEC v1.0

Vivado Design Suite Release 2023.2

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Resource figures are taken from the utilization report issued at the end of implementation using the Out-of-Context flow in Vivado Design Suite.
The Out-of-Context IP constraints include HD.CLK_SRC properties as required to ensure correct hold timing closure: these properties are enabled using the Tcl command: set_param ips.includeClockLocationConstraints true
Maximum frequency is measured using the Out-of-Context flow to synthesize and implement the IP instance in isolation. This ensures that the design is not distorted in order to route to device pins.
Maximum frequency is the result of a binary search of attempted clock period constraints. The reported figure is the highest frequency at which the design met timing.
Maximum frequency is determined for one clock input, while other clock inputs have fixed frequencies. The fixed clocks and their frequencies are stated for each test case.
LUT figures do not include LUTs used as pack-thrus, but do include LUTs used as memory.
Default Vivado Design Suite 2023.2 settings were used. You may be able to improve on these figures using different settings. Because surrounding circuitry will affect placement and timing, no guarantee can be given that these figures will be repeatable in a larger design.

Data is provided for the following device families:

Kintex UltraScale+
Virtex UltraScale
Virtex UltraScale+

Kintex UltraScale+

Part Information			Configuration Parameters			Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	Exdes_Seed	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcku11p	ffva1156	2	xckup_rx		tx_clk=425	rx_clk	812	1903	1483	0	0	0	PRODUCTION 1.29 05-01-2022
xcku11p	ffva1156	2	xckup_tx		rx_clk=425	tx_clk	869	1795	1471	0	0	0	PRODUCTION 1.29 05-01-2022

Virtex UltraScale

Part Information			Configuration Parameters			Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	Exdes_Seed	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcvu065	ffvc1517	2	xcvu_rx		tx_clk=425	rx_clk	593	1861	1471	0	0	0	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	2	xcvu_tx		rx_clk=425	tx_clk	635	1818	1471	0	0	0	PRODUCTION 1.27 12-04-2018

Virtex UltraScale+

Part Information			Configuration Parameters			Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	Exdes_Seed	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcvu3p	ffvc1517	2	xcvup_rx		tx_clk=425	rx_clk	790	1896	1476	0	0	0	PRODUCTION 1.28 03-30-2022
xcvu3p	ffvc1517	2	xcvup_tx		rx_clk=425	tx_clk	865	1792	1471	0	0	0	PRODUCTION 1.28 03-30-2022

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