Resource Utilization for MIPI D-PHY v4.3

Vivado Design Suite Release 2020.2

Interpreting the results

This page contains resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Kintex-7

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
C_DPHY_LANES
C_HS_LINE_RATE
C_EN_7S_LINERATE_CHECK
C_LPX_PERIOD
C_STABLE_CLK_PERIOD
C_ESC_CLK_PERIOD
C_HS_TIMEOUT
C_ESC_TIMEOUT
C_EN_DEBUG_REGS
C_EXAMPLE_SIMULATION
C_DPHY_MODE
C_EN_REG_IF
SupportLevel
C_EN_TIMEOUT_REGS
Fixed clocks (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs MMCME2_ADV PLLE2_ADV BUFR Speedfile Status
xc7k325t ffg900 -3 series7__rx_1 1 1000 true 50 200.000 20.000 65541 25600 false false SLAVE false false clk_hs_rxp=500 core_clk=200 rxbyteclkhs=100 380 255 0 0 0 0 0 1 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -3 series7__rx_2 2 1000 true 50 200.000 20.000 65541 25600 false false SLAVE false false clk_hs_rxp=500 core_clk=200 rxbyteclkhs=100 648 426 0 0 0 0 0 1 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -3 series7__rx_3 3 1000 true 50 200.000 20.000 65541 25600 false false SLAVE false false clk_hs_rxp=500 core_clk=200 rxbyteclkhs=100 953 596 0 0 0 0 0 1 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -3 series7__rx_4 4 1000 true 50 200.000 20.000 65541 25600 false false SLAVE false 1 false clk_hs_rxp=500 core_clk=200 rxbyteclkhs=100 1288 767 0 0 0 0 0 1 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -3 series7__tx_1 1 1000 true 50 200.000 20.000 65541 25600 false false MASTER false false core_clk=200 oserdes_clk90_in=400 oserdes_clk_in=400 oserdes_clkdiv_in=100 txbyteclkhs_in=100 txclkesc_in=20 425 454 0 0 0 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -3 series7__tx_2 2 1000 true 50 200.000 20.000 65541 25600 false false MASTER false false core_clk=200 oserdes_clk90_in=400 oserdes_clk_in=400 oserdes_clkdiv_in=100 txbyteclkhs_in=100 txclkesc_in=20 632 589 0 0 0 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -3 series7__tx_3 3 1000 true 50 200.000 20.000 65541 25600 false false MASTER false false core_clk=200 oserdes_clk90_in=400 oserdes_clk_in=400 oserdes_clkdiv_in=100 txbyteclkhs_in=100 txclkesc_in=20 808 724 0 0 0 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 -3 series7__tx_4 4 1000 true 50 200.000 20.000 65541 25600 false false MASTER false 1 false core_clk=200 oserdes_clk90_out=400 oserdes_clk_out=400 oserdes_clkdiv_out=100 txbyteclkhs=100 txclkesc_out=20 1050 906 0 0 0 1 0 2 PRODUCTION 1.12 2017-02-17

Zynq UltraScale+

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
C_DPHY_LANES
C_HS_LINE_RATE
C_EN_7S_LINERATE_CHECK
C_LPX_PERIOD
C_STABLE_CLK_PERIOD
C_ESC_CLK_PERIOD
C_HS_TIMEOUT
C_ESC_TIMEOUT
C_EN_DEBUG_REGS
C_EXAMPLE_SIMULATION
C_DPHY_MODE
C_EN_REG_IF
SupportLevel
C_EN_TIMEOUT_REGS
Fixed clocks (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs MMCM PLL BUFGCE Speedfile Status
xczu9eg ffvb1156 -2 uplus__rx_1 1 1000 50 200.000 20.000 65541 25600 false false SLAVE false false clk_rxp=500 clkoutphy_in=1000 core_clk=200 rxbyteclkhs=100 428 312 0 0 0 0 0 1 PRODUCTION 1.29 08-03-2020
xczu9eg ffvb1156 -2 uplus__rx_2 2 1000 50 200.000 20.000 65541 25600 false false SLAVE false false clk_rxp=500 clkoutphy_in=1000 core_clk=200 rxbyteclkhs=100 724 487 0 0 0 0 0 1 PRODUCTION 1.29 08-03-2020
xczu9eg ffvb1156 -2 uplus__rx_3 3 1000 50 200.000 20.000 65541 25600 false false SLAVE false false clk_rxp=500 clkoutphy_in=1000 core_clk=200 rxbyteclkhs=100 1025 661 0 0 0 0 0 1 PRODUCTION 1.29 08-03-2020
xczu9eg ffvb1156 -2 uplus__rx_4 4 1000 50 200.000 20.000 65541 25600 false false SLAVE false 1 false clk_rxp=500 clkoutphy_out=1499 core_clk=200 rxbyteclkhs=100 1362 868 0 0 0 0 1 2 PRODUCTION 1.29 08-03-2020
xczu9eg ffvb1156 -2 uplus__rx_5 4 2500 50 200.000 20.000 65541 25600 false false SLAVE false 1 false clk_rxp=1250 clkoutphy_out=1499 core_clk=200 rxbyteclkhs=100 1362 869 0 0 0 1 1 4 PRODUCTION 1.29 08-03-2020
xczu9eg ffvb1156 -2 uplus__tx_1 1 1000 50 200.000 20.000 65541 25600 false false MASTER false false clkoutphy_in=1000 core_clk=200 txbyteclkhs_in=100 txclkesc_in=20 560 598 0 0 0 0 0 0 PRODUCTION 1.29 08-03-2020
xczu9eg ffvb1156 -2 uplus__tx_2 2 1000 50 200.000 20.000 65541 25600 false false MASTER false false clkoutphy_in=1000 core_clk=200 txbyteclkhs_in=100 txclkesc_in=20 806 807 0 0 0 0 0 0 PRODUCTION 1.29 08-03-2020
xczu9eg ffvb1156 -2 uplus__tx_3 3 1000 50 200.000 20.000 65541 25600 false false MASTER false false clkoutphy_in=1000 core_clk=200 txbyteclkhs_in=100 txclkesc_in=20 1052 1020 0 0 0 0 0 0 PRODUCTION 1.29 08-03-2020
xczu9eg ffvb1156 -2 uplus__tx_4 4 1000 50 200.000 20.000 65541 25600 false false MASTER false 1 false clkoutphy_out=1499 core_clk=200 txbyteclkhs=100 txclkesc_out=20 1308 1270 0 0 0 1 1 4 PRODUCTION 1.29 08-03-2020
xczu9eg ffvb1156 -2 uplus__tx_5 1 500 50 200.000 20.000 65541 25600 false false MASTER false 1 false clkoutphy_out=1499 core_clk=200 txbyteclkhs=100 txclkesc_out=20 574 660 0 0 0 1 1 5 PRODUCTION 1.29 08-03-2020
xczu9eg ffvb1156 -2 uplus__tx_6 4 2500 50 200.000 20.000 65541 25600 false false MASTER false 1 false clkoutphy_out=1499 core_clk=200 txbyteclkhs=100 txclkesc_out=20 1293 1270 0 0 0 1 1 4 PRODUCTION 1.29 08-03-2020

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