Performance and Resource Utilization for Viterbi Decoder v9.1

Vivado Design Suite Release 2020.2

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Kintex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Viterbi_Type
Channels
Architecture
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7k480t ffg901 -1 k7_1_par_ch1 Standard 1 Parallel aclk 281 2214 1721 0 2 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_par_ch3 Multi_Channel 3 Parallel aclk 358 2281 3519 0 2 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_ser_ch1 Standard 1 Serial aclk 380 1488 1932 0 2 0 PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Viterbi_Type
Channels
Architecture
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcku115 flva1517 -1 ku_1_par_ch1 Standard 1 Parallel aclk 358 2310 1735 0 2 0 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_par_ch3 Multi_Channel 3 Parallel aclk 450 2024 3517 0 2 0 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_ser_ch1 Standard 1 Serial aclk 450 1378 1942 0 2 0 PRODUCTION 1.26 12-04-2018

Kintex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Viterbi_Type
Channels
Architecture
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcku13p ffve900 -1 kup_1_par_ch1 Standard 1 Parallel aclk 516 2283 1743 0 2 0 PRODUCTION 1.28 02-27-2020
xcku13p ffve900 -1 kup_1_par_ch3 Multi_Channel 3 Parallel aclk 571 2170 3520 0 2 0 PRODUCTION 1.28 02-27-2020
xcku13p ffve900 -1 kup_1_ser_ch1 Standard 1 Serial aclk 571 1484 2057 0 2 0 PRODUCTION 1.28 02-27-2020

Versal ACAP

These results are preliminary and based on advanced speedfiles in 2020.2. As production speedfiles are made available and QoR tuning has occurred, the performance will improve. The 2021.1 numbers will be more representative of what can be expected in production.

It is also important to compare the same speedgrade and voltage. These numbers are for low voltage -1 speedgrade VC1902, running at 0.7V. Results from other families are running at higher voltages.

Note that for Versal ACAPs, the performance of the adaptable engines are expected to be similar to the PL performance of 16nm devices. Using the hard IP in Versal enables higher overall system level performance or lower overall power consumption.

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Viterbi_Type
Channels
Architecture
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvm1802 vfvc1760 1LP ver_1_par_ch1 Standard 1 Parallel aclk 363 1920 1719 0 2 0 ENGINEERING-SAMPLE 1.04 10-18-2020
xcvm1802 vfvc1760 1LP ver_1_par_ch3 Multi_Channel 3 Parallel aclk 489 2045 3518 0 2 0 ENGINEERING-SAMPLE 1.04 10-18-2020
xcvm1802 vfvc1760 1LP ver_1_ser_ch1 Standard 1 Serial aclk 494 1324 1939 0 2 0 ENGINEERING-SAMPLE 1.04 10-18-2020

Virtex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Viterbi_Type
Channels
Architecture
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7vx690t ffg1157 -1 v7_1_par_ch1 Standard 1 Parallel aclk 265 2172 1720 0 2 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_par_ch3 Multi_Channel 3 Parallel aclk 358 2282 3518 0 2 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_ser_ch1 Standard 1 Serial aclk 369 1356 1932 0 2 0 PRODUCTION 1.11 2014-09-11

Virtex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Viterbi_Type
Channels
Architecture
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu160 flgb2104 -1 vu_1_par_ch1 Standard 1 Parallel aclk 352 2228 1759 0 2 0 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_par_ch3 Multi_Channel 3 Parallel aclk 456 2025 3518 0 2 0 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_ser_ch1 Standard 1 Serial aclk 456 1379 1970 0 2 0 PRODUCTION 1.27 12-04-2018

Virtex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Viterbi_Type
Channels
Architecture
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu9p flgb2104 -1 vup_1_par_ch1 Standard 1 Parallel aclk 522 2295 1752 0 2 0 PRODUCTION 1.27 02-28-2020
xcvu9p flgb2104 -1 vup_1_par_ch3 Multi_Channel 3 Parallel aclk 571 2168 3520 0 2 0 PRODUCTION 1.27 02-28-2020
xcvu9p flgb2104 -1 vup_1_ser_ch1 Standard 1 Serial aclk 571 1486 2058 0 2 0 PRODUCTION 1.27 02-28-2020

Zynq UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Viterbi_Type
Channels
Architecture
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xczu9eg ffvb1156 -1 zup_1_par_ch1 Standard 1 Parallel aclk 538 2308 1755 0 2 0 PRODUCTION 1.29 08-03-2020
xczu9eg ffvb1156 -1 zup_1_par_ch3 Multi_Channel 3 Parallel aclk 571 2168 3519 0 2 0 PRODUCTION 1.29 08-03-2020
xczu9eg ffvb1156 -1 zup_1_ser_ch1 Standard 1 Serial aclk 571 1488 2058 0 2 0 PRODUCTION 1.29 08-03-2020

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