Zynq UltraScale+ Devices Register Reference > Module Summary > DDR_QOS_CTRL Module > DDRC_URGENT (DDR_QOS_CTRL) Register

DDRC_URGENT (DDR_QOS_CTRL) Register

DDRC_URGENT (DDR_QOS_CTRL) Register Description

Register NameDDRC_URGENT
Relative Address0x0000000510
Absolute Address 0x00FD090510 (DDR_QOS_CTRL)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionDDRC URGENT Sideband signal control register

DDRC_URGENT (DDR_QOS_CTRL) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:14razRead as zero0x0Reserved for future use
ARURGENT_513rwNormal read/write0x0Sideband signal to indicate a DDRC Port 5 read queue urgent transaction. When asserted, if DDRC.rd_port_urgent_en register is set, causes the port arbiter to switch immediately to read.
AWURGENT_512rwNormal read/write0x0Sideband signal to indicate a DDRC Port 5 write urgent transaction. When asserted, if DDRC.wr_port_urgent_en register is set, causes the port arbiter to switch immediately to write.
ARURGENT_411rwNormal read/write0x0Sideband signal to indicate a DDRC Port 4 read queue urgent transaction. When asserted, if DDRC.rd_port_urgent_en register is set, causes the port arbiter to switch immediately to read.
AWURGENT_410rwNormal read/write0x0Sideband signal to indicate a DDRC Port 4 write urgent transaction. When asserted, if wr_port_urgent_en register is set, causes the port arbiter to switch immediately to write.
ARURGENT_3 9rwNormal read/write0x0Sideband signal to indicate a DDRC Port 3 read queue urgent transaction. When asserted, if DDRC.rd_port_urgent_en register is set, causes the port arbiter to switch immediately to read.
AWURGENT_3 8rwNormal read/write0x0Sideband signal to indicate a DDRC Port 3 write urgent transaction. When asserted, if DDRC.wr_port_urgent_en register is set, causes the port arbiter to switch immediately to write.
ARURGENTR_2 7rwNormal read/write0x0Sideband signal to indicate a DDRC Port 2 read red queue urgent transaction. When asserted, if DDRC.rd_port_urgent_en register is set, causes the port arbiter to switch immediately to read.
ARURGENTB_2 6rwNormal read/write0x0Sideband signal to indicate a DDRC Port 2 read blue queue urgent transaction. When asserted, if DDRC.rd_port_urgent_en register is set, causes the port arbiter to switch immediately to read.
AWURGENT_2 5rwNormal read/write0x0Sideband signal to indicate a DDRC Port 2 write urgent transaction. When asserted, if DDRC.wr_port_urgent_en register is set, causes the port arbiter to switch immediately to write.
ARURGENTR_1 4rwNormal read/write0x0Sideband signal to indicate a DDRC Port 1 read red queue urgent transaction. When asserted, if DDRC.rd_port_urgent_en register is set, causes the port arbiter to switch immediately to read.
ARURGENTB_1 3rwNormal read/write0x0Sideband signal to indicate a DDRC Port 1 read blue queue urgent transaction. When asserted, if DDRC.rd_port_urgent_en register is set, causes the port arbiter to switch immediately to read.
AWURGENT_1 2rwNormal read/write0x0Sideband signal to indicate a DDRC Port 1 write urgent transaction. When asserted, if DDRC.wr_port_urgent_en register is set, causes the port arbiter to switch immediately to write.
ARURGENT_0 1rwNormal read/write0x0Sideband signal to indicate a DDRC Port 0 read queue urgent transaction. When asserted, if DDRC.rd_port_urgent_en register is set, causes the port arbiter to switch immediately to read.
AWURGENT_0 0rwNormal read/write0x0Sideband signal to indicate a DDRC Port 0 write urgent transaction. When asserted, if DDRC.wr_port_urgent_en register is set, causes the port arbiter to switch immediately to write.