Field Name | Bits | Type | Reset Value | Description |
Reserved | 31:14 | razRead as zero | 0x0 | Reserved for future use |
ARURGENT_5 | 13 | rwNormal read/write | 0x0 | Sideband signal to indicate a DDRC Port 5 read queue urgent transaction. When asserted, if DDRC.rd_port_urgent_en register is set, causes the port arbiter to switch immediately to read. |
AWURGENT_5 | 12 | rwNormal read/write | 0x0 | Sideband signal to indicate a DDRC Port 5 write urgent transaction. When asserted, if DDRC.wr_port_urgent_en register is set, causes the port arbiter to switch immediately to write. |
ARURGENT_4 | 11 | rwNormal read/write | 0x0 | Sideband signal to indicate a DDRC Port 4 read queue urgent transaction. When asserted, if DDRC.rd_port_urgent_en register is set, causes the port arbiter to switch immediately to read. |
AWURGENT_4 | 10 | rwNormal read/write | 0x0 | Sideband signal to indicate a DDRC Port 4 write urgent transaction. When asserted, if wr_port_urgent_en register is set, causes the port arbiter to switch immediately to write. |
ARURGENT_3 | 9 | rwNormal read/write | 0x0 | Sideband signal to indicate a DDRC Port 3 read queue urgent transaction. When asserted, if DDRC.rd_port_urgent_en register is set, causes the port arbiter to switch immediately to read. |
AWURGENT_3 | 8 | rwNormal read/write | 0x0 | Sideband signal to indicate a DDRC Port 3 write urgent transaction. When asserted, if DDRC.wr_port_urgent_en register is set, causes the port arbiter to switch immediately to write. |
ARURGENTR_2 | 7 | rwNormal read/write | 0x0 | Sideband signal to indicate a DDRC Port 2 read red queue urgent transaction. When asserted, if DDRC.rd_port_urgent_en register is set, causes the port arbiter to switch immediately to read. |
ARURGENTB_2 | 6 | rwNormal read/write | 0x0 | Sideband signal to indicate a DDRC Port 2 read blue queue urgent transaction. When asserted, if DDRC.rd_port_urgent_en register is set, causes the port arbiter to switch immediately to read. |
AWURGENT_2 | 5 | rwNormal read/write | 0x0 | Sideband signal to indicate a DDRC Port 2 write urgent transaction. When asserted, if DDRC.wr_port_urgent_en register is set, causes the port arbiter to switch immediately to write. |
ARURGENTR_1 | 4 | rwNormal read/write | 0x0 | Sideband signal to indicate a DDRC Port 1 read red queue urgent transaction. When asserted, if DDRC.rd_port_urgent_en register is set, causes the port arbiter to switch immediately to read. |
ARURGENTB_1 | 3 | rwNormal read/write | 0x0 | Sideband signal to indicate a DDRC Port 1 read blue queue urgent transaction. When asserted, if DDRC.rd_port_urgent_en register is set, causes the port arbiter to switch immediately to read. |
AWURGENT_1 | 2 | rwNormal read/write | 0x0 | Sideband signal to indicate a DDRC Port 1 write urgent transaction. When asserted, if DDRC.wr_port_urgent_en register is set, causes the port arbiter to switch immediately to write. |
ARURGENT_0 | 1 | rwNormal read/write | 0x0 | Sideband signal to indicate a DDRC Port 0 read queue urgent transaction. When asserted, if DDRC.rd_port_urgent_en register is set, causes the port arbiter to switch immediately to read. |
AWURGENT_0 | 0 | rwNormal read/write | 0x0 | Sideband signal to indicate a DDRC Port 0 write urgent transaction. When asserted, if DDRC.wr_port_urgent_en register is set, causes the port arbiter to switch immediately to write. |