Zynq UltraScale+ Devices Register Reference > Module Summary > DDR_QOS_CTRL Module > QOS_CTRL (DDR_QOS_CTRL) Register

QOS_CTRL (DDR_QOS_CTRL) Register

QOS_CTRL (DDR_QOS_CTRL) Register Description

Register NameQOS_CTRL
Relative Address0x0000000004
Absolute Address 0x00FD090004 (DDR_QOS_CTRL)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00400000
DescriptionSet Port Type Register

QOS_CTRL (DDR_QOS_CTRL) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:23razRead as zero0x0Reserved for future use
APB_ERR_RES22rwNormal read/write0x1When an APB (register) access occurs to an unimplemented space (there is no register at that location), the resulting pslverr will be:
0: pslverr = 1'b0
1: pslverr = 1'b1
There is also a maskable interrupt , "INV_APB" that could be asserted, independent of what option is selected here.
PORT5_WR_CTRL21rwNormal read/write0x0Port 5 QoS throttle Control on Write channel
0 - Disable
1 - Enable
PORT5_HPR_CTRL20rwNormal read/write0x0Port 5 QoS throttle Control on Read HPR channel
0 - Disable
1 - Enable
PORT5_LPR_CTRL19rwNormal read/write0x0Port 5 QoS throttle Control on Read LPR channel
0 - Disable
1 - Enable
PORT4_WR_CTRL18rwNormal read/write0x0Port 4 QoS throttle Control on Write channel
0 - Disable
1 - Enable
PORT4_HPR_CTRL17rwNormal read/write0x0Port 4 QoS throttle Control on Read HPR channel
0 - Disable
1 - Enable
PORT4_LPR_CTRL16rwNormal read/write0x0Port 4 QoS throttle Control on Read LPR channel
0 - Disable
1 - Enable
PORT3_WR_CTRL15rwNormal read/write0x0Port 3 QoS throttle Control on Write channel
0 - Disable
1 - Enable
PORT3_HPR_CTRL14rwNormal read/write0x0Port 3 QoS throttle Control on Read HPR channel
0 - Disable
1 - Enable
PORT3_LPR_CTRL13rwNormal read/write0x0Port 3 QoS throttle Control on Read LPR channel
0 - Disable
1 - Enable
PORT2_WR_CTRL12rwNormal read/write0x0Port 2 QoS throttle Control on Write channel
0 - Disable
1 - Enable
PORT2B_HPR_CTRL11rwNormal read/write0x0Port 2 Blue Queue QoS throttle Control on Read HPR channel
0 - Disable
1 - Enable
PORT2B_LPR_CTRL10rwNormal read/write0x0Port 2 Blue Queue throttle Control on Read LPR channel
0 - Disable
1 - Enable
PORT2R_HPR_CTRL 9rwNormal read/write0x0Port 2 Red Queue QoS throttle Control on Read HPR channel
0 - Disable
1 - Enable
PORT2R_LPR_CTRL 8rwNormal read/write0x0Port 2 Red Queue QoS throttle Control on Read LPR channel
0 - Disable
1 - Enable
PORT1_WR_CTRL 7rwNormal read/write0x0Port 1 QoS throttle Control on Write channel
0 - Disable
1 - Enable
PORT1B_HPR_CTRL 6rwNormal read/write0x0Port 1 Blue Queue throttle QoS Control on Read HPR channel
0 - Disable
1 - Enable
PORT1B_LPR_CTRL 5rwNormal read/write0x0Port 1 Blue Queue throttle Control on Read LPR channel
0 - Disable
1 - Enable
PORT1R_HPR_CTRL 4rwNormal read/write0x0Port 1 Red Queue QoS throttle Control on Read HPR channel
0 - Disable
1 - Enable
PORT1R_LPR_CTRL 3rwNormal read/write0x0Port 1 Red Queue QoS throttle Control on Read LPR channel
0 - Disable
1 - Enable
PORT0_WR_CTRL 2rwNormal read/write0x0Port 0 QoS throttle Control on Write channel
0 - Disable
1 - Enable
PORT0_HPR_CTRL 1rwNormal read/write0x0Port 0 QoS throttle Control on Read HPR channel
0 - Disable
1 - Enable
PORT0_LPR_CTRL 0rwNormal read/write0x0Port 0 QoS throttle Control on Read LPR channel
0 - Disable
1 - Enable