Zynq UltraScale+ Devices Register Reference > Module Summary > DDRC Module > ADDRMAP0 (DDRC) Register

ADDRMAP0 (DDRC) Register

ADDRMAP0 (DDRC) Register Description

Register NameADDRMAP0
Relative Address0x0000000200
Absolute Address 0x00FD070200 (DDRC)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionAddress Map Register 0

This register is static. Static registers can only be written when the controller is in reset.

ADDRMAP0 (DDRC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
addrmap_cs_bit0 4:0rwNormal read/write0x0Selects the HIF address bit used as rank address bit 0.
Valid Range: 0 to 27, and 31
Internal Base: 6
The selected HIF address bit is determined by adding the internal base to the value of this field.
If set to 31, rank address bit 0 is set to 0.