Zynq UltraScale+ Devices Register Reference > Module Summary > DDRC Module > ADDRMAP0 (DDRC) Register
|Absolute Address||0x00FD070200 (DDRC)|
|Description||Address Map Register 0|
This register is static. Static registers can only be written when the controller is in reset.
|Field Name||Bits||Type||Reset Value||Description|
|addrmap_cs_bit0||4:0||rwNormal read/write||0x0||Selects the HIF address bit used as rank address bit 0.|
Valid Range: 0 to 27, and 31
Internal Base: 6
The selected HIF address bit is determined by adding the internal base to the value of this field.
If set to 31, rank address bit 0 is set to 0.