Zynq UltraScale+ Devices Register Reference > Module Summary > DDRC Module > ADDRMAP1 (DDRC) Register

ADDRMAP1 (DDRC) Register

ADDRMAP1 (DDRC) Register Description

Register NameADDRMAP1
Relative Address0x0000000204
Absolute Address 0x00FD070204 (DDRC)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionAddress Map Register 1

This register is static. Static registers can only be written when the controller is in reset.

ADDRMAP1 (DDRC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
addrmap_bank_b220:16rwNormal read/write0x0Selects the HIF address bit used as bank address bit 2.
Valid Range: 0 to 29 and 31
Internal Base: 4
The selected HIF address bit is determined by adding the internal base to the value of this field.
If set to 31, bank address bit 2 is set to 0.
addrmap_bank_b112:8rwNormal read/write0x0Selects the HIF address bits used as bank address bit 1.
Valid Range: 0 to 30
Internal Base: 3
The selected HIF address bit for each of the bank address bits is determined by adding the internal base to the value of this field.
addrmap_bank_b0 4:0rwNormal read/write0x0Selects the HIF address bits used as bank address bit 0.
Valid Range: 0 to 30
Internal Base: 2
The selected HIF address bit for each of the bank address bits is determined by adding the internal base to the value of this field.