Zynq UltraScale+ Devices Register Reference > Module Summary > DDRC Module > ADDRMAP10 (DDRC) Register

ADDRMAP10 (DDRC) Register

ADDRMAP10 (DDRC) Register Description

Register NameADDRMAP10
Relative Address0x0000000228
Absolute Address 0x00FD070228 (DDRC)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionAddress Map Register 10

This register is static. Static registers can only be written when the controller is in reset.

ADDRMAP10 (DDRC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
addrmap_row_b927:24rwNormal read/write0x0Selects the HIF address bits used as row address bit 9.
Valid Range: 0 to 11
Internal Base: 15
The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. This register field is used only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
addrmap_row_b819:16rwNormal read/write0x0Selects the HIF address bits used as row address bit 8.
Valid Range: 0 to 11
Internal Base: 14
The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. This register field is used only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
addrmap_row_b711:8rwNormal read/write0x0Selects the HIF address bits used as row address bit 7.
Valid Range: 0 to 11
Internal Base: 13
The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. This register field is used only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
addrmap_row_b6 3:0rwNormal read/write0x0Selects the HIF address bits used as row address bit 6.
Valid Range: 0 to 11
Internal Base: 12
The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. This register field is used only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.