Zynq UltraScale+ Devices Register Reference > Module Summary > DDRC Module > ADDRMAP3 (DDRC) Register

ADDRMAP3 (DDRC) Register

ADDRMAP3 (DDRC) Register Description

Register NameADDRMAP3
Relative Address0x000000020C
Absolute Address 0x00FD07020C (DDRC)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionAddress Map Register 3

This register is static. Static registers can only be written when the controller is in reset.

ADDRMAP3 (DDRC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
addrmap_col_b927:24rwNormal read/write0x0- Full bus width mode: Selects the HIF address bit used as column address bit 9.
- Half bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR3 mode).
- Quarter bus width mode: Selects the HIF address bit used as column address bit 13.
Valid Range: 0 to 7, and 15
Internal Base: 9
The selected HIF address bit is determined by adding the internal base to the value of this field.
If set to 15, this column address bit is set to 0.
Note: Per JEDEC DDR3 specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.
In LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is used.
addrmap_col_b819:16rwNormal read/write0x0- Full bus width mode: Selects the HIF address bit used as column address bit 8.
- Half bus width mode: Selects the HIF address bit used as column address bit 9.
- Quarter bus width mode: Selects the HIF address bit used as column address bit 11.
Valid Range: 0 to 7, and 15
Internal Base: 8
The selected HIF address bit is determined by adding the internal base to the value of this field.
If set to 15, this column address bit is set to 0.
Note: Per JEDEC DDR3 specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.
In LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is used.
addrmap_col_b711:8rwNormal read/write0x0- Full bus width mode: Selects the HIF address bit used as column address bit 7.
- Half bus width mode: Selects the HIF address bit used as column address bit 8.
- Quarter bus width mode: Selects the HIF address bit used as column address bit 9.
Valid Range: 0 to 7, and 15
Internal Base: 7
The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0.
addrmap_col_b6 3:0rwNormal read/write0x0- Full bus width mode: Selects the HIF address bit used as column address bit 6.
- Half bus width mode: Selects the HIF address bit used as column address bit 7.
- Quarter bus width mode: Selects the HIF address bit used as column address bit 8.
Valid Range: 0 to 7, and 15
Internal Base: 6
The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0.