Zynq UltraScale+ Devices Register Reference > Module Summary > DDRC Module > ADDRMAP4 (DDRC) Register

ADDRMAP4 (DDRC) Register

ADDRMAP4 (DDRC) Register Description

Register NameADDRMAP4
Relative Address0x0000000210
Absolute Address 0x00FD070210 (DDRC)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionAddress Map Register 4

This register is static. Static registers can only be written when the controller is in reset.

ADDRMAP4 (DDRC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
addrmap_col_b1111:8rwNormal read/write0x0- Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR3 mode).
- Half bus width mode: Unused. To make it unused, this should be tied to 4'hF.
- Quarter bus width mode: Unused. To make it unused, this should be tied to 4'hF.
Valid Range: 0 to 7, and 15
Internal Base: 11
The selected HIF address bit is determined by adding the internal base to the value of this field.
If set to 15, this column address bit is set to 0.
Note: Per JEDEC DDR3 specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.
In LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is used.
addrmap_col_b10 3:0rwNormal read/write0x0- Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR3 mode).
- Half bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR3 mode).
- Quarter bus width mode: Unused. To make it unused, this should be tied to 4'hF.
Valid Range: 0 to 7, and 15
Internal Base: 10
The selected HIF address bit is determined by adding the internal base to the value of this field.
If set to 15, this column address bit is set to 0.
Note: Per JEDEC DDR3 specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.
In LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is used.